Features
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Low-power Operation Including Special STOP Mode
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Frequency: 16.78 MHz at 5V ± 10% Supply and 20.97 MHz at 5V ± 5%, Software
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Programmable
Technology: 1
µ
High-density Complementary Metal-Oxide Semiconductor (HCMOS),
Static Design
Package: 132-pin Ceramic Leaded Chip Carrier (CERQUAD) and 132-pin Ceramic Pin
Grid Array (PGA)
Modular Architecture in a Single Chip
CPU: 32-bit 6800 Family (Upward Object-code Compatible with The 68010)
New Instructions For Controller Applications
Intelligent 16-bit Timer
– 16 Independent, Programmable Channels
– Any Channel Can Perform Any Time Function (For Example Input Capture, Output
Compare, Pulse Width Modulation, etc.)
– Two timer Count Registers with 2-bit Programmable Prescalers
– Selectable Channel Priority Levels
– Reduced CPU Intervention
– RISC like CPU within the TPU
Two Serial I/O Subsystems
– Enhanced 68HC11-type Serial Communications Interface (SCI) Universal
Asynchronous Receiver Transmitter (UART) with Parity
– Enhanced 68HC11-type Serial Peripheral Interface with I/O RAM Queue (QSPI)
On-chip Memory: 2-Kbytes Standby RAM
On-chip, Programmable, Chip-select Logic
– Up to 12 Signals for Memory and Peripheral Interface with I/O Select
System Failure Protection
– 68HC11-type Computer Operating Properly (COP) Watchdog Timer
– 68HC11-type Periodic Interrupt Timer
– 68000 Family Spurious Interrupt, Halt, and Bus Time-out Monitors
Up to 48 Discrete I/O Pins
High-
performance
32-bit Integrated
Microcontroller
TS68332
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1. Description
The TS68332 is a 32-bit microcontroller, combining high-performance data manipula-
tion capabilities with powerful peripheral subsystems. The TS68332 is the first
member of the 68300 family of modular embedded controllers featuring fully static,
high-speed complementary metal-oxide semiconductor technology. Based on the
powerful TS68020, the CPU32 instruction processing module provides enhanced sys-
tem performance and utilizes the extensive software base of the 68000 family.
2118A–HIREL–11/05
Screening/Quality
This product is manufactured in full compliance with:
• MIL-STD-883 (class B)
• DSCC 5962-91501
• Or according to Atmel-Grenoble standard
R suffix
PGA 132
Ceramic Pin Grid Array
A suffix
CERQUAD 132
Ceramic Leaded Chip Carrier
2. Introduction
Figure 2-1 on page 3
is a block diagram of the TS68332 showing the major components. The pin
descriptions are provided in
Table 2-1 on page 6.
The TS68332 contains intelligent peripheral
modules such as the Time Processor Unit (TPU), which provides 16 microcoded channels for
performing time-related activities from simple input capture or output compare to complicated
motor control or pulse width modulation. High-speed serial communications are provided by the
Queued Serial Module (QSM) with synchronous and asynchronous protocols available. 2-
Kbytes of fully static standby RAM allow fast two-cycle access for system and data stacks and
variable storage with provision for battery back-up. There is a System Integration Module (SIM)
which includes twelve chip selects to enhance system integration for fast external memory or
peripheral access. The powerful 32-bit CPU (CPU 32) is based on the industry-standard
TS68020. These modules are connected on chip via the Intermodule Bus (IMB) and provide
reduced system part count, size, cost of implementation and increased reliability.
2
TS68332
2118A–HIREL–11/05
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