74F192 Up/Down Decade Counter with Separate Up/Down Clocks
April 1988
Revised September 2000
74F192
Up/Down Decade Counter
with Separate Up/Down Clocks
General Description
The 74F192 is an up/down BCD decade (8421) counter.
Separate Count Up and Count Down Clocks are used, and
in either counting mode the circuits operate synchronously.
The outputs change state synchronously with the
LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down
outputs are used as the clocks for a subsequent stage
without extra logic, thus simplifying multistage counter
designs. Individual preset inputs allow the circuit to be used
as a programmable counter. Both the Parallel Load (PL)
and the Master Reset (MR) inputs asynchronously override
the clocks.
Features
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number
74F192SJ
(Note 1)
74F192PC
Package Number
M16D
N16E
Package Description
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Note 1:
Device not available in Tape and Reel.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009496
www.fairchildsemi.com
74F192
Unit Loading/Fan Out
U.L.
Pin Names
CP
U
CP
D
MR
PL
P
0
–P
3
Q
0
–Q
3
TC
D
TC
U
Description
HIGH/LOW
Count Up Clock Input (Active Rising Edge)
Count Down Clock Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Asynchronous Parallel Load Input (Active LOW)
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count Down (Borrow) Output (Active LOW)
Terminal Count Up (Carry) Output (Active LOW)
1.0/3.0
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
1.8 mA
20
µ
A/
−
1.8 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
1 mA/20 mA
−
1 mA/20 mA
−
1 mA/20 mA
Functional Description
The 74F192 is an asynchronously presettable decade
counter. It contains four edge-triggered flip-flops, with inter-
nal gating and steering logic to provide master reset, indi-
vidual preset, count up and count down operations.
A LOW-to-HIGH transition on the CP input to each flip-flop
causes the output to change state. Synchronous switching,
as opposed to ripple counting, is achieved by driving the
steering gates of all stages from a common Count Up line
and a common Count Down line, thereby causing all state
changes to be initiated simultaneously. A LOW-to-HIGH
transition on the Count Up input will advance the count by
one; a similar transition on the Count Down input will
decrease the count by one. While counting with one clock
input, the other should be held HIGH, as indicated in the
Function Table. Otherwise, the circuit will either count by
twos or not at all, depending on the state of the first flip-
flop, which cannot toggle as long as either clock input is
LOW.
The Terminal Count Up (TC
U
) and Terminal Count Down
(TC
D
) outputs are normally HIGH. When the circuit has
reached the maximum count state 9, the next HIGH-to-
LOW transition of the Count Up Clock will cause TC
U
to go
LOW. TC
U
will stay LOW until CP
U
goes HIGH again, thus
effectively repeating the Count Up Clock, but delayed by
two gate delays. Similarly, the TC
D
output will go LOW
when the circuit is in the zero state and the Count Down
Clock goes LOW. Since the TC outputs repeat the clock
waveforms, they can be used as the clock input signals to
the next higher order circuit in a multistage counter.
TC
U
=
Q
0
• Q
3
• CP
U
TC
D
=
Q
0
• Q
1
• Q
2
• Q
3
• CP
D
The 74F192 has an asynchronous parallel load capability
permitting the counter to be preset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW, informa-
tion present on the Parallel Data input (P
0
–P
3
) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs. A HIGH signal on the
Master Reset input will disable the preset gates, override
both clock inputs, and latch each Q output in the LOW
state. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of
that clock will be interpreted as a legitimate signal and will
be counted.
Function Table
MR
H
L
L
L
L
PL
X
L
H
H
H
CP
U
X
X
CP
D
X
X
H
Mode
Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
Count Down
H
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
H
State Diagram
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2
74F192
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Output HIGH Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
−60
38
4.75
3.75
−0.6
−1.8
−150
55
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V, Except CP
u
, CP
D
V
IN
=
0.5V, CP
u
, CP
D
V
OUT
=
0V
V
O
=
LOW
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