Edition 2010-02
Published by
Infineon Technologies AG
81726 Munich, Germany
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
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of any third party.
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©
2010 Infineon Technologies AG
XC886/888CLM
XC886/888 User’s Manual
Revision History: V1.3 2010-02
Previous Versions: V1.0, V1.1, V1.2
Page
2-9
7-11
7-12
7-13
7-14
10-3
12-31
14-3
16-6
Subjects (major changes since last revision)
Footnote on instruction cycles is added.
Figure 7-6 on CGU block diagram is updated.
PLL loss of lock recovery sequence is updated.
Select external oscillator sequence is updated.
Note on PLL base mode is updated.
The wording ‘integer’ is removed since normalization always involves a 32-
bit variable.
Direction of RXD (slave) signal in Figure 12-11 is corrected.
Handling of T12 period register is elaborated.
Conversion time example is updated.
Changes from V1.2 2009-04 to V1.3 2010-02
16-39, 16-
SFR address formula for CHCTRx, RESRxL/H and RESRAxL/H registers
53
are corrected.
18-19
Header block of LIN BSL Modes 0/2/8 is corrected
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
User’s Manual
V1.3, 2010-02
XC886/888CLM
Table of Contents
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.3
3
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.1.1
3.5.2
3.5.2.1
3.5.3
3.5.4
3.5.4.1
3.5.5
3.5.5.1
3.5.5.2
3.5.5.3
3.5.5.4
Page
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Reserved, Undefined and Unimplemented Terminology . . . . . . . . . . . . . 1-19
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Processor Architecture
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
CPU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Extended Operation (EO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Power Control (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Memory Organization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Compatibility between Flash and ROM devices . . . . . . . . . . . . . . . . . . . . 3-3
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
System Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Bit-Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
XC886/888 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
I-1
V1.3, 2010-02
User’s Manual
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