RD74LVC244B
Octal Buffers / Line Drivers with 3-state Outputs
REJ03D0220–0200
Rev.2.00
Feb. 17, 2005
Description
The RD74LVC244B has eight line drivers with three state outputs in a 20 pin package. This device is a non-inverting
buffer and has two active low enables (1G and 2G). Each enable independently controls four buffers. Low voltage and
high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption
extends the life of a battery for long time operation.
Features
•
•
•
•
•
•
V
CC
= 1.65 V to 5.5 V
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
OUT
(Max.) = 5.5 V (@V
CC
= 0 V or output off state)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current ±4 mA (@V
CC
= 1.65 V)
±8 mA (@V
CC
= 2.3 V)
±12 mA (@V
CC
= 2.7 V)
±24 mA (@V
CC
= 3.0 V to 5.5 V)
•
Ordering Information
Part Name
RD74LVC244BFPEL
RD74LVC244BTELL
Package Type
SOP–20 pin (JEITA)
TSSOP–20 pin
Package Code
(Previous Code)
PRSP0020DD–B
(FP–20DAV)
PTSP0020JB–A
(TTP–20DAV)
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
G
H
L
L
H: High level
L: Low level
X: Immaterial
Z: High impedance
A
X
H
L
Output Y
Z
H
L
Rev.2.00 Feb. 17, 2005 page 1 of 8
RD74LVC244B
Pin Arrangement
1G 1
1A1 2
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
GND 10
20 V
CC
19 2G
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
(Top view)
Absolute Maximum Ratings
Item
Supply voltage
Input diode current
Input voltage
Output diode current
Output voltage
Output current
V
CC
, GND current / pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
or I
GND
Tstg
Ratings
–0.5 to 7.0
–50
–0.5 to 7.0
–50
50
–0.5 to V
CC
+0.5
–0.5 to 6.0
±50
100
–65 to +150
V
V
mA
mA
°C
Unit
V
mA
V
mA
V
O
= –0.5 V
V
O
= V
CC
+0.5 V
Output "H" or "L"
Output "Z" or V
CC
:OFF
V
I
= –0.5 V
Conditions
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.2.00 Feb. 17, 2005 page 2 of 8
RD74LVC244B
Recommended Operating Conditions
Item
Supply voltage
Input / Output voltage
Symbol
V
CC
V
I
V
O
Operating temperature
Output current
Ta
I
OH
Ratings
1.5 to 5.5
1.65 to 5.5
0 to 5.5
0 to V
CC
0 to 5.5
–40 to 85
–4
–8
–12
–24
I
OL
4
8
12
24
Input rise / fall time
*1
Unit
V
V
Conditions
Data hold
At operation
G,
A
Output “H” or “L”
Output “Z” or V
CC
: OFF
°C
mA
V
CC
= 1.65 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 5.5 V
mA
V
CC
= 1.65 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 5.5 V
ns/V
V
CC
= 1.65 V to 2.7 V
V
CC
= 3.0 V to 5.5 V
t
r
, t
f
20
10
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Rev.2.00 Feb. 17, 2005 page 3 of 8
RD74LVC244B
Electrical Characteristics
Ta = –40 to 85°C
Item
Input voltage
Symbol
V
IH
V
CC
(V)
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
V
IL
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
Output voltage
V
OH
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
V
OL
1.65 to 5.5
1.65
2.3
2.7
3.0
4.5
Input current
Output leak current
Off state output
current
Quiescent supply
current
I
IN
I
OFF
I
OZ
I
CC
∆I
CC
0 to 5.5
0
2.7 to 5.5
2.7 to 3.6
2.7 to 5.5
2.7 to 3.6
Min
V
CC
×0.65
1.7
2.0
V
CC
×0.7
—
—
—
—
V
CC
–0.2
1.2
1.7
2.2
2.4
2.2
3.8
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
V
CC
×0.35
0.7
0.8
V
CC
×0.3
—
—
—
—
—
—
—
0.2
0.45
0.7
0.4
0.55
0.55
±5.0
±5.0
±5.0
±5.0
5.0
500
µA
µA
µA
µA
µA
V
IN
= 5.5 V or GND
V
IN
/ V
OUT
= 5.5 V
V
IN
= V
CC
or GND
V
O
= 5.5 V or GND
V
IN
= 3.6 V to 5.5 V
V
IN
= V
CC
or GND
V
IN
= one input at
(V
CC
–0.6)V,
other inputs at V
CC
or GND
V
I
OL
= 100 µA
I
OL
= 4 mA
I
OL
= 8 mA
I
OL
= 12 mA
I
OL
= 24 mA
I
OH
= –24 mA
V
I
OH
= –100 µA
I
OH
= –4 mA
I
OH
= –8 mA
I
OH
= –12 mA
V
Unit
V
Test Conditions
Rev.2.00 Feb. 17, 2005 page 4 of 8
RD74LVC244B
Switching Characteristics
Ta = –40 to 85°C
Item
Propagation delay time
Symbol
t
PLH
t
PHL
V
CC
(V)
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
Output enable time
t
ZH
t
ZL
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
Output disable time
t
HZ
t
LZ
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
Between output pins skew*
1
From
Unit
ns
A
(Input)
Y
To
(Output)
Min
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.0
1.5
1.0
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.0
8.0
Max
10.9
7.9
6.9
5.9
4.4
12.6
9.6
8.6
7.6
6.1
12.1
7.8
6.8
6.5
5.5
—
—
—
1.0
1.0
—
—
ns
G
Y
ns
G
Y
t
OSLH
t
OSHL
1.8±0.15
2.5±0.2
2.7
3.3±0.3
5.0±0.5
ns
Input capacitance
Output capacitance
Note:
C
IN
C
O
3.3
3.3
pF
pF
1. This parameter is characterized but not tested.
t
OSLH
= | t
PLHm
– t
PLHn
|, t
OSHL
= | t
PHLm
– t
PHLn
|
Operating Characteristics
Ta = 25°C
Item
Power dissipation
Capacitance
Symbol
C
PD
V
CC
(V)
1.8
2.5
3.3
5.0
Min
—
—
—
—
Typ
25
25
27
32
Max
—
—
—
—
Unit
pF
Test conditions
f = 10 MHz
Rev.2.00 Feb. 17, 2005 page 5 of 8
FPGA/CPLD
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