or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1
tn1112_01.1
Lattice Semiconductor
Test Device:
ispMACH 4128V
I/O Standard:
LVCMOS 3.3V with input bus-hold latch turned on
Temperature:
Room temperature
External Input
Circuit
None
Method 1
Input Series
Resistor
—
100
Ω
1K
Ω
4.7K
Ω
Method 2
100
Ω
1K
Ω
Method 3
100
Ω
1K
Ω
Feedback Resistor or
Capacitor
—
—
—
—
1K
Ω
560
Ω
10K
Ω
33pF
100pF
33pF
Input Hysteresis in
Lattice CPLD and FPGA Devices
t
RISE
<100ns
220ns
2µs
6µs
800ns
700ns
5µs
700ns
2µs
5µs
t
FALL
<100ns
155ns
1.5µs
7µs
300ns
350ns
1.9µs
350ns
600ns
1.5µs
The plots below are measured with MachXO. A 680
Ω
resistor is used in Method 1. The I/Os are configured as “bus-
hold”.
Figure 4. Test Setup
A
B
MachXO
with
Bus-Hold Input
In
680
Out
In the following figures, top trace represents outputs and bottom trace represents inputs. Persistence was set to 5
seconds for all waveforms.
2
Lattice Semiconductor
Figure 5. Input Measured at Point A
Input Hysteresis in
Lattice CPLD and FPGA Devices
Figure 6. Zoomed View of Rising Edge of Figure 5
3
Lattice Semiconductor
Input Hysteresis in
Lattice CPLD and FPGA Devices
Input Hysteresis
Figure 7 demonstrates the input signal with slow ramp rate virtually follow the ramp rate of MachXO output.
Figure 7. Input measured at Point B
Note “jump” at transition point.
Figure 8. Zoomed View of Rising Edge of Figure 7
Most digital circuitry is effectively linear in nature. The output normally swings from one extreme (VOL) to the other
(VOH). At threshold level a smallest amount of noise will cause the output to swing widely from one extreme to the
other.
4
Lattice Semiconductor
Input Hysteresis in
Lattice CPLD and FPGA Devices
With a fast slew rate input, the signal will stay around the threshold region for a short time. With a slower signal,
which stays in the threshold region for a long time, the noise will have more time to reverse the signal direction.
Hysteresis is one common solution to this problem. Hysteresis means that the state of the output is not only depen-
dent on the state of the input but, also, on the immediate past history of the input. A Schmitt trigger adds hysteresis
to the input by creating different trip points for low-to-high and high-to-low transition. For the CPLDs and FPGAs
that do not have the Schmitt trigger input, the bus-hold latch with an external resistor works in a similar manner.
The bus-hold input circuitry works by sinking a small amount of current when it's below the threshold and sourcing
when it's above the threshold. This means that the input voltage tends to stay low when it's low and high when it's
high. If all of the I/Os on a bus go high impedance, the bus will tend to stay in the same state until an output turns
on.
If a resistor is inserted in series with the input, the change in current will result in change in the voltage seen at the
pin. This is what causes that jump. The optimum resistor value will cause enough
Δ
V to put the input well past the
threshold region so that noise will not be able to cause unwanted switching, but will not be so large as to exacer-
bate the noise or slow the signal.
Refer to Figure 9 for discussion of the 'jump'.
The voltage jump is 128mV at the output (Ch3) transition point.
When the input is below the threshold, the voltage across the resistor is 96mV and -32mV after the transition. In
other words, the input signal source must source 144µA (96mV/680
Ω
). When input A passes the threshold, the sig-
nal source sinks 47µA (-32mV/680
Ω
). At this point, any noise spike is unlikely to go back beyond the threshold.
Figure 9. Input Series Resistor and Hysteresis
Summary
As the data indicate, even with the very simple input series resistor used in Method 1 and the CPLD internal input
bus-hold latch, maximum input rise and fall times will extend to hundreds of nanoseconds to microseconds.
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