Low Skew, ÷1, ÷2
LVCMOS/LVTTL Clock Generator
G
ENERAL
D
ESCRIPTION
The 8701 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Clock
Generator . The low impedance LVCMOS outputs are
designed to drive 50Ω series or parallel ter minated
transmission lines. The effective fanout can be increased from
20 to 40 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in
the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The
bank enable inputs, BANK_EN0:1, support enabling and
disabling each bank of outputs individually. The master
reset input, nMR/OE, resets the internal frequency dividers and
also controls the active and high impedance states of all outputs.
The 8701 is character ized at 3.3V and mixed
3.3V input supply, and 2.5V output supply operating
modes. Guaranteed bank, output and part-to-part skew
characteristics make the 8701 ideal for those clock
d i s t r i bu t i o n a p p l i c a t i o n s d e m a n d i n g w e l l d e f i n e d
performance and repeatability.
8701
DATASHEET
F
EATURES
• Twenty LVCMOS outputs, 7Ω typical output impedance
• One LVCMOS/LVTTL clock input
• Maximum output frequency: 250MHz
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• Output skew: 250ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 200ps (maximum)
• Multiple frequency skew: 300ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
• Available in lead-free RoHS compliant package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
8701 REVISION F JANUARY 21, 2015
1
©2015 Integrated Device Technology, Inc.
8701 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
2, 5, 11,
26, 32, 35, 41,
44
7, 9, 18, 21,
28, 30, 37, 39,
46, 48
16, 20
25, 27, 29,
31, 33
34, 36, 38,
40, 42
43, 45, 47,
1, 3
4, 6, 8,
10, 12
22
Name
V
DDO
Power
Type
Description
Output supply pins.
GND
V
DD
QA0, QA1, QA2,
QA3, QA4
QB0, QB1, QB2,
QB3, QB4
QC0, QC1, QC2,
QC3, QC4
QD0, QD1, QD2,
QD3, QD4
CLK
Power
Power
Power supply ground.
Positive supply pins.
Bank A outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank B outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank C outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank D outputs. LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Input Pulldown LVCMOS / LVTTL clock input.
Controls frequency division for Bank D outputs.
13
DIV_SELD
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank C outputs.
14
DIV_SELC
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank B outputs.
23
DIV_SELB
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank A outputs.
24
DIV_SELA
Input
Pullup
LVCMOS / LVTTLinterface levels.
Enables and disables outputs by banks.
BANK_EN1,
17, 19
Input
Pullup
BANK_EN0
LVCMOS / LVTTLinterface levels.
Master Reset and output enable. When HIGH, output drivers are
15
nMR/OE
Input
Pullup enabled. Whe LOW, output drivers are in HiZ and dividers are reset.
LVCMOS / LVTTLinterface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
LOW SKEW, ÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
2
REVISION F 1/21/15
8701 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
95
Units
V
V
V
mA
LOW SKEW, ÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
4
REVISION F 1/21/15
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