Differential-to-3.3V LVPECL
Zero Delay/Multiplier/Divider
G
ENERAL
D
ESCRIPTION
The 873995 is a Zero Delay/Multiplier/Divider with hitless input clock
switching capability and a member of the family of low jitter/phase
noise devices from IDT. The 873995 is ideal for use in redundant,
fault tolerant clock trees where low phase noise and low jitter are
critical. The device receives two differential LVPECL clock signals
from which it generates 6 LVPECL clock outputs with “zero” delay.
The out-put divider and feedback divider selections also allow for
frequency multiplication or division.
The 873995 Dynamic Clock Switch (DCS) circuit continuously
monitors both input clock signals. Upon detection of a failure (input
clock stuck LOW or HIGH for at least 1 period), INP_BAD for that
clock will be set HIGH. If that clock is the primary clock, the DCS will
switch to the good secondary clock and phase/frequency alignment
will occur with minimal output phase disturbance.
The low jitter characteristics combined with input clock monitoring
and automatic switching from bad to good input clocks make the
873995 an ideal choice for mission criti-cal applications that utilize
1G or 10G Ethernet or 1G/4G/10G Fibre Channel.
873995
DATA SHEET
F
EATURES
•
Six differential 3.3V LVPECL outputs
•
Selectable differential clock inputs
•
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Input clock frequency range: 49MHz to 213.33MHz
•
Output clock frequency range: 49MHz to 640MHz
•
VCO range: 490MHz to 640MHz
•
External feedback for “zero delay” clock regeneration
with configurable frequencies
•
Output skew: 100ps (maximum)
•
RMS phase jitter (1.875MHz - 20MHz): 0.77ps (typical) assum-
ing a low phase noise reference clock input
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
•
Use replacement part 873996AYLF
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
873995 REVISION A 8/25/15
1
©2015 Integrated Device Technology, Inc.
873995 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
Name
PLL_SEL
Input
Type
Pullup
Description
Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock.When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
Active LOW Master Reset. When logic LOW, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic HIGH, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
When HIGH-to-LOW, resets the input bad flags and aligns CLK_INDI-
CATOR to SEL_CLK. LVCMOS / LVTTL interface levels.
Negative supply pins.
Pulldown Non-inverting differential clock input.
Pullup/
Inverting differential clock input. V
CC
/2 default when left floating.
Pulldown
Pulldown Non-inverting differential clock input.
Pullup/
Inverting differential clock input. V
CC
/2 default when left floating.
Pulldown
Pulldown Differential external feedback.
Pullup/
Differential external feedback. V
CC
/2 default when left floating.
Pulldown
Selects the primary reference clock. When LOW, selects CLK0 as the
Pulldown primary clock source. When HIGH, selects CLK1 as the primary clock
source. LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup
Pullup
Bank B output divider control pins. LVCMOS / LVTTL interface levels.
Bank A output divider control pins. LVCMOS / LVTTL interface levels.
Output supply voltage for B Bank outputs.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply voltage for A Bank outputs.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply voltage for FB outputs.
Feedback outputs. LVPECL interface levels.
Analog supply pin.
Pullup
Feedback divider control pins. LVCMOS / LVTTL interface levels.
Clock indicator pin. When LOW, CLK0, nCLK0 is selected, when HIGH,
CLK1, nCLK1 is selected. LVCMOS / LVTTL interface levels.
Indicates detection of a bad input reference clock 0 with respect to the
feedback signal. The output is active HIGH.
LVCMOS / LVTTL interface levels.
2
nMR
Input
Pullup
3
4, 12, 17
5
6
7
8
9
10
11
13, 47
14, 15, 16
18, 19, 20
21, 28
22, 23
24, 25
26, 27
29, 36
30, 31
32, 33
34, 35
37
38, 39
40
41, 42,
43
44
45
nINIT
V
EE
CLK0
nCLK0
CLK1
nCLK1
EXT_FB
nEXT_FB
SEL_CLK
V
CC
NB0, NB1, NB2
NA0, NA1, NA2
V
CCO_B
nQB2, QB2
nQB1, QB1
nQB0, QB0
V
CCO_A
nQA2, QA2
nQA1, QA1
nQA0, QA0
V
CCO_FB
QFB, nQFB
V
CCA
NFB0, NFB1, NFB2
CLK_INDICATOR
INP0BAD
Input
Power
Input
Input
Input
Input
Input
Input
Input
Power
Input
Input
Power
Output
Output
Output
Power
Output
Output
Output
Power
Output
Power
Input
Output
Output
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION A 8/25/15
2
DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
873995 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
,
CONTINUED
Number
46
Name
INP1BAD
Type
Output
Description
48
MAN_OVERRIDE
Input
Indicates detection of a bad input reference clock 1 with respect to the
feedback signal. The output is active HIGH.
LVCMOS / LVTTL interface levels.
Manual override. When HIGH, disables internal clock switch circuitry
Pulldown and CLK_INDICATOR will track SEL_CLK. When LOW, Dynamic Clock
Switch is enabled. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. F
EEDBACK
D
IVIDER
F
UNCTION
T
ABLE
NFB[2:0]
000
001
010
011
100
101
110
111
Feedback Divider Value
1
2
3
4
5
6
8
10
Output Frequency Range
N/A
NOTE1
N/A
NOTE1
163.33MHz - 200MHz
122.5MHz - 160MHz
98MHz - 128MHz
81.66MHz - 106.66MHz
61.25MHz - 80MHz
49MHz - 64MHz
NOTE 1: The Phase Detector has a maximum frequency limit of 200MHz, so these values cannot be used for feedback. The
reason these options are available is for applications that use an output on Bank A or Bank B for feedback and the QFB/
nQFB pair for a high frequency output. For example, a user may need two 62.5MHz outputs, three 125MHz outputs and one
625MHz output from a 62.5MHz reference clock. For this case, the user would use one of the Bank A Outputs for feedback
and set the bank for /10, and use the other two Bank A Outputs to drive the 2 loads. The Bank B Output Divider would be set
for /5, and the Feedback Divider would be set for /1.
T
ABLE
3B. NA/NB B
ANK
D
IVIDER
F
UNCTION
T
ABLE
NA[2:0], NB[2:0]
000
001
010
011
100
101
110
111
Bank A/B Divider Value
1
2
3
4
5
6
8
10
Output Frequency Range
490MHz - 640MHz
245MHz - 320MHz
163.33MHz - 213.33MHz
122.5MHz - 160MHz
98MHz - 128MHz
81.66MHz - 106.66MHz
61.25MHz - 80MHz
49MHz - 64MHz
REVISION A 8/25/15
3
DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
873995 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
31.8°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= V
CCO_FB
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO_A, _B, _FB
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.15
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
300
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
LVCMOS Inputs
LVCMOS Inputs
NA[2:0], NB[2:0],
NFB[2:0], PLL_SEL,
nINIT, nMR
SEL_CLK, MAN_OVER-
RIDE
NA[2:0], NB[2:0],
NFB[2:0], PLL_SEL,
nINIT, nMR
SEL_CLK, MAN_OVER-
RIDE
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
I
IH
Input High Current
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= V
CCO_FB
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
Parameter
Input High Current
CLK0, CLK1, EXT_
FB
nCLK0, nCLK1,
nEXT_FB
CLK0, CLK1, EXT_
FB
nCLK0, nCLK1,
nEXT_FB
Test Conditions
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-150
0.15
V
EE
+ 0.5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is V
CC
+ 0.3V.
REVISION A 8/25/15
4
DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
873995 DATA SHEET
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= V
CCO_FB
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO_X
- 1.4
V
CCO_X
- 2.0
0.6
Typical
Maximum
V
CCO_X
- 0.9
V
CCO_X
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to VCCO_A, _B, _FB = - 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= V
CCO_FB
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
VCO
t(Ø)
tjit(ø)
tsk(o)
tsk(b)
Parameter
PLL VCO Lock Range
Static Phase Offset; NOTE 2
RMS Phase Jitter (Random); NOTE 7
Output Skew; NOTE 3
Bank Skew; NOTE 4
62.5MHz Output;
NOTE 1, 5
125MHz Output;
NOTE 1, 5
62.5MHz Output;
NOTE 1, 6
125MHz Output;
NOTE 1, 6
30
Tested at
typical conditions
60
45
90
M>2
odc
t
R /
t
F
Output Duty Cycle
Output Rise/Fall Time
M=2
M=1
20% to 80%
47
45
40
250
53
55
60
600
PLL_SEL = HIGH
Test Conditions
Minimum
490
60
0.77
100
80
Typical
Maximum
640
Units
MHz
ps
ps
ps
ps
ps/cycle
ps/cycle
ps/cycle
ps/cycle
%
%
%
ps
Δ
PER/CYCLE
Rate of change
of Periods
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: These parameters are guaranteed by characterization. Not tested in production.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 5: Specification holds for a clock switch between two signals no greater than 400ps out of phase.
Delta period change per cycle is averaged over the clock switch excursion.
NOTE 6: Specification holds for a clock switch between two signals greater than 400ps out of phase.
Delta period change per cycle is averaged over the clock switch excursion.
NOTE 7: Please refer to the Phase Noise Plot.
REVISION A 8/25/15
5
DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
