Data Sheet, Rev. 1.30, Apr. 2006
Cover Page
HYS64T256020HU–[3/3S]–A
HYS72T256020HU–[3/3S]–A
HYS64T256020HU–[3.7/5]–A
HYS72T256020HU–[3.7/5]–A
240-Pin Unbuffered DDR2 SDRAM Modules
UDIMM
DDR2 SDRAM
RoHS Compliant
Memory Products
Imprint
Edition 2006-04
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©
Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Revision History
HYS64T256020HU–[3/3S]–A, HYS72T256020HU–[3/3S]–A, HYS64T256020HU–[3.7/5]–A
HYS72T256020HU–[3.7/5]–A
Revision History: 2006-04, Rev. 1.30
Previous Version: Rev. 1.20 2005-08
Page
7
5
24
26
39
33
Subjects (major changes since last revision)
added PC2–5300 product types
added performace tables
added speed grade definitions
updated AC Timing parametere
added tables for
I
DD
test conditions
updated
I
DD
currents
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send us your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_s_rev321 / 3 / 2005-10-05
HYS[64/72]T256xxxHU–[3/…/5]–A
Unbuffered DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
2
2.1
2.2
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
4
5
6
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations and Block Diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
DD
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
DD
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
23
24
24
26
32
33
39
41
SPD Codes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Data Sheet
4
Rev. 1.30, 2006-04
02182004-TRHM-8N4H
240-Pin Unbuffered DDR2 SDRAM Modules
UDIMM
HYS64T256020HU–[3/3S]–A
HYS72T256020HU–[3/3S]–A
HYS64T256020HU–[3.7/5]–A
HYS72T256020HU–[3.7/5]–A
1
Overview
This chapter gives an overview of the 240-Pin Unbuffered DDR2 SDRAM Modules product family and describes
its main characteristics.
1.1
•
•
•
•
•
Features
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Average Refresh Period 7.8
µs
at a
T
CASE
lower
than 85°C, 3.9µs between 85°C and 95°C.
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and
On-Die Termination (ODT)
Serial Presence Detect with E
2
PROM
Dimensions (nominal):
30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Card
“B”,”E” and “G“
RoHS compliant products
1)
•
240-Pin PC2-5300 and PC2-4200 DDR2 SDRAM
memory modules
256M
×
64 non-ECC and 256M
×
72 ECC module
organization, and 128M
×
8 chip organization
2GByte modules built with 1-Gbit DDR2 SDRAMs in
P-TFBGA-68 chipsize packages
All Speed grades faster than DDR2-400 comply
with DDR2-400 timing specifications.
Standard Double-Data-Rate-Two Synchronous
DRAMs (DDR2 SDRAM) with a single + 1.8 V
(± 0.1 V) power supply
Programmable CAS Latencies (3, 4 and 5), Burst
Length (8 & 4) and Burst Type
Performance tables
•
•
•
Table 1 “Performance table for PC2–5300” on Page 5
Table 2 “Performance table for PC2–4200–444” on Page 6
Table 3 “Performance table for PC2–3200 3–3–3” on Page 6
Performance table for PC2–5300
–3
PC2–5300 4–4–4
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
–3S
PC2–5300 5–5–5
333
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
Table 1
Product Type Speed Code
Speed Grade
max. Clock Frequency
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
333
333
200
12
12
45
57
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
Data Sheet
5
Rev. 1.30, 2006-04
02182004-TRHM-8N4H
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