October 2006
HYS[64/72]T256020EU–[25F/2.5]–B
HYS[64/72]T256020EU–[3/3S]–B
HYS[64/72]T256020EU–3.7–B
240-Pin unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
UDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
HYS[64/72]T256020EU–[25F/2.5]–B, HYS[64/72]T256020EU–[3/3S]–B, HYS[64/72]T256020EU–3.7–B
Revision History: 2006-10, Rev. 1.0
Page
All
17–18
36–38
All
23
All
43, 44
Subjects (major changes since last revision)
Adapted internet edition
Updated Clock Load Tables and Notes of Block Diagrams
I
DD
currents update
Qimonda update
Modified AC Timing Parameters
Updated for speed -5
Added IDD Current Values for speed -3S and -3.7
Previous Revision: 2006-09, Rev. 0.61
Previous Revision: 2006-08, Rev. 0.6
Previous Revision: Rev. 0.5
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
10262006-SX8C-DEY8
2
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E
2
PROM
UDIMM and EDIMM Dimensions (nominal):
30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Card “E” and
“G”
RoHS compliant products
1)
• 240-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2
SDRAM memory modules.
• 256M
×
64 and 256M
×72
module organization,and
128M
×
8 chip organization
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• 2 GB Built with 1Gbit DDR2 SDRAMs in and
P-TFBGA-68-6 chipsize packages
• All speed grades faster than DDR400 comply with
DDR400 timing specifications.
• Programmable CAS Latencies (3, 4, 5 and 6), Burst
Length (8 & 4) and Burst Type
• Average Refresh Period 7.8
µs
at a
T
CASE
lower than 85°C,
3.9µs between 85°C and 95°C.
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–25F
PC2–6400
5–5–5
–2.5
PC2–6400
6–6–6
400
333
266
200
15
15
45
60
–3
PC2–5300
4–4–4
–
333
333
200
12
12
45
57
–3S
PC2–5300
5–5–5
–
333
266
200
15
15
45
60
–3.7
PC2–4200
4–4–4
–
266
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
f
CK6
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
400
400
266
200
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.0, 2006-10
10262006-SX8C-DEY8
3
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
1.2
Description
are mounted on the PCB board. The DIMMs feature serial
presence detect based on a serial E
2
PROM device using the
2-pin I
2
C protocol. The first 128 bytes are programmed with
configuration data and are write protected; the second
128 bytes are available to the customer.
The QIMONDA HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
module family are unbuffered DIMM modules “UDIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 256M
×
64 (2 GB) and as
ECC modules in 256M
×
72 (2 GB) organization and density,
intended for mounting into 240-pin connector sockets.
The memory array is designed with 1-Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. Decoupling capacitors
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–6400
HYS64T256020EU–25F–B
HYS72T256020EU–25F–B
PC2–6400
HYS64T256020EU–2.5–B
HYS72T256020EU–2.5–B
PC2–5300
HYS64T256020EU–3–B
HYS72T256020EU–3–B
PC2–5300
HYS64T256020EU–3S–B
HYS72T256020EU–3S–B
PC2–4200
HYS64T256020EU–3.7–B
HYS72T256020EU–3.7–B
2 GB 2R×8 PC2–4200U–444–12–E0
2 GB 2R×8 PC2–4200E–444–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
2 GB 2R×8 PC2–5300U–555–12–E0
2 GB 2R×8 PC2–5300E–555–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
2 GB 2R×8 PC2–5300U–444–12–E0
2 GB 2R×8 PC2–5300E–444–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
2 GB 2R×8 PC2–6400U–666–12–E0
2 GB 2R×8 PC2–6400E–666–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
2 GB 2R×8 PC2–6400U–555–12–E0
2 GB 2R×8 PC2–6400E–555–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
Compliance Code
2)
Description
SDRAM
Technology
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T256020EU–3.7–B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
Chapter 6
of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–12–E0”, where
4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card “B”.
Rev. 1.0, 2006-10
10262006-SX8C-DEY8
4
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 3
Address Format
DIMM
Density
2 GByte
2 GByte
Module
Organization
128M
×
64
128M
×
72
Memory
Ranks
2
2
ECC/
Non-ECC
Non-ECC
ECC
# of SDRAMs # of row/bank/column
bits
16
18
14/3/10
14/3/10
Raw
Card
E
G
TABLE 4
Components on Modules
Product Type
1)
HYS64T256020EU
HYS72T256020EU
DRAM Components
1)
HYB18T1G800BF
HYB18T1G800BF
DRAM Density
1 Gbit
1 Gbit
DRAM Organisation
128M
×
8
128M
×
8
Note
2)
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2006-10
10262006-SX8C-DEY8
5
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