Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Revision History
Revision History: 2007-02-09, Rev. 1.2
All
Page 4
Page 20
Adapted internet edition
Updated
“Ordering Information (Pb-free components and assembly)” on Page 4
Updated
“Current Spec. and Conditions” on Page 20
Previous Revision: 2006-08-18, Rev. 1.1
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2
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
1
1.1
Overview
Features
• Detects errors on the channel and reports them to the host
memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Automatic Channel Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• Hot Add-on and Hot Remove Capability.
• MBIST and IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Low profile: 133.35mm x 30.35 mm
• 240 Pin gold plated card connector with 1.00 mm contact
centers (JEDEC standard pending).
• Based on JEDEC standard reference card designs (Jedec
standard pending).
• SPD (Serial Presence Detect) with 256 Byte serial
E
2
PROM.Performance:
• RoHS Compliant Products
1)
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
• 240-pin Fully-Buffered ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation and Server
main memory applications.
• Module organisation one rank 64M
×
72,
one rank 128M
×
72, two ranks 128M
×
72,
two ranks 256M
×72
• JEDEC Standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V
(± 0.1 V) power supply.
• Built with 512Mb DDR2 SDRAMs in 60-ball FBGA
Chipsize Packages.
• Re-drive and re-sync of all address, command, clock and
data signals using AMB (Advanced Memory Buffer).
• High-Speed Differential Point-to-Point Link Interface at
1.5 V (Jedec standard pending).
• Host Interface and AMB component industry standard
compliant.
• Supports SMBus protocol interface for access to the AMB
configuration registers.
TABLE 1
Performance for DDR2–667
Product Type Speed Code
Speed Grade
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
–3S
PC2–5300 5–5–5
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
333
266
200
15
15
45
60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.2, 2006-02
09142006-Q5TN-B9NE
3
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
1.2
Description
using an Industry Standard High-Speed Differential Point-to-
Point Link Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host, including
memory request initiation, timing, refresh, scrubbing, sparing,
configuration access, and power management. The
Advanced Memory Buffer interface is responsible for handling
channel and memory requests to and from the local DIMM
and for forwarding requests to other DIMMs on the memory
channel. Fully Buffered DIMM provides a high memory
bandwidth, large capacity channel solution that has a narrow
host interface. The maximum memory capacity is 288 DDR2
SDRAM devices per channel or 8 DIMMs.
This document describes the electrical and mechanical
features of a 240-pin, PC2-5300F ECC type, Fully Buffered
Double-Data-Rate Two Synchronous DRAM Dual In-Line
Memory Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered
DIMMs use commodity DRAMs isolated from the memory
channel behind a buffer on the DIMM. They are intended for
use as main memory when installed in systems such as
servers and workstations. PC2-5300 refers to the DIMM
naming convention indicating the DDR2 SDRAMs running at
333 MHz clock speed and offering 5300 MB/s peak
bandwidth. FB-DIMM features a novel architecture including
the Advanced Memory Buffer. This single chip component,
located in the center of each DIMM, acts as a repeater and
buffer for all signals and commands which are exchanged
between the host controller and the DDR2 SDRAMs including
data in- and output. The AMB communicates with the host
controller and / or the adjacent DIMMs on a system board
TABLE 2
Ordering Information (Pb-free components and assembly)
Product Type
1)
PC2-5300F (DDR2-667):
HYS72T64400HFD–3S–B
HYS72T64500HFD–3S–B
HYS72T128420HFD–3S–B
HYS72T128520HFD–3S–B
HYS72T256420HFD–3S–B
HYS72T256520HFD–3S–B
512MB 1Rx8 PC2–4200F–444–11–A
512MB 1Rx8 PC2–4200F–444–11–A
1GB 2Rx8 PC2–4200F–444–11–B
1GB 2Rx8 PC2–4200F–444–11–B
2GB 2Rx4 PC2–4200F–444–11–H
2GB 2Rx4 PC2–4200F–444–11–H
1 Rank, FB-DIMM
1 Rank, FB-DIMM
2 Ranks, FB-DIMM
2 Ranks, FB-DIMM
2 Ranks, FB-DIMM
2 Ranks, FB-DIMM
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×4)
512 Mbit (×4)
Compliance Code
2)
Description
SDRAM Technology
1) All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HFA-3.7-A, indicating Rev. A dice
are used for DDR2 SDRAM components. To learn more on QIMONDA DDR2 module and component nomenclature see
Chapter 8
of this
datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2-4200F-444-11-A”, where 4200F means
Fully Buffered DIMM with 4.26 GB/sec. Module Bandwidth and “444-11” means CAS latency = 4, t
rcd
latency = 4 and t
rp
latency = 4 using
JEDEC SPD Revision 1.1 and assembled on Raw Card “A”.
TABLE 3
Address Format
DIMM
Density
512 MB
1 GB
2 GB
Module
Organization
64M
×72
128M
×72
256M
×72
Memory
Ranks
1
2
2
ECC/
Non-ECC
ECC
ECC
ECC
# of
SDRAMs
9
18
36
# of row/bank/columns bits
13/2/10
13/2/10
13/2/11
Raw
Card
A
B
H
Rev. 1.2, 2006-02
09142006-Q5TN-B9NE
4
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