October 2007
HYS72T512420EFA–[25F/3S]–C
240-Pin Fully-Buffered DDR2 SDRAM Modules
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev.1.20
Internet Data Sheet
HYS72T512420EFA–[25F/3S]–C
Fully-Buffered DDR2 SDRAM Modules
Revision History: Rev.1.20, 2007-10-19
Page 5
Page 20
Page 20
Page 65
Page 5
Page 20
Changed
Table 4 “Components on Modules” on Page 5
Changed
Table 5.1 “I
CC
/I
DD
Conditions” on Page 20
Changed
Table 14 “I
CC
/I
DD
Specification for PC2-6400F” on Page 20
Changed
Table 21 “I
CC
/I
DD
Specification for PC2-5300F” on Page 65
Changed
Table 2 “Ordering Information for RoHS Compliant Products” on Page 5.
Updated
Table 5.1 “I
CC
/I
DD
Conditions” on Page 20
Previous Revision: Rev. 1.10, 2007-08-22
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03202007-06NE-DYYI
2
Internet Data Sheet
HYS72T512420EFA–[25F/3S]–C
Fully-Buffered DDR2 SDRAM Modules
1
1.1
Overview
Features
• Detects errors on the channel and reports them to the host
memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Automatic Channel Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• Hot Add-on and Hot Remove Capability.
• MBIST and IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Low profile: 133.35mm x 30.35 mm
• 240 Pin gold plated card connector with 1.00mm contact
centers (JEDEC standard pending).
• Based on JEDEC standard reference card designs (Jedec
standard pending).
• SPD (Serial Presence Detect) with 256 Byte serial
E
2
PROM.Performance:
• RoHS Compliant Products
1)
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
• 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM
Module for PC, Workstation and Server main memory
applications.
• two rank 512M
×
72 module organization, and 256M
×
4,
128M
×
4 chip organization
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• 4GB Modules built with chipsize packages PG-TFBGA-60
• Re-drive and re-sync of all address, command, clock and
data signals using AMB (Advanced Memory Buffer).
• High-Speed Differential Point-to-Point Link Interface at 1.5
V (Jedec standard pending).
• Host Interface and AMB component industry standard
compliant.
• Supports SMBus protocol interface for access to the AMB
configuration registers.
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL5
CL4
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–25F
DDR2–800D
PC2–6400D
5–5–5
–3S
DDR2–667D
PC2–5300D
5–5–5
200
333
266
15
15
45
60
MHz
MHz
MHz
ns
ns
ns
ns
Unit
f
CK3
f
CK5
f
CK4
t
RCD
t
RP
t
RAS
t
RC
200
400
266
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev.1.20, 2007-10-19
03202007-06NE-DYYI
3
Internet Data Sheet
HYS72T512420EFA–[25F/3S]–C
Fully-Buffered DDR2 SDRAM Modules
1.2
Description
controller and / or the adjacent DIMMs on a system board
using an Industry Standard High-Speed Differential Point-to-
Point Link Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host, including
memory request initiation, timing, refresh, scrubbing, sparing,
configuration access, and power management. The
Advanced Memory Buffer interface is responsible for handling
channel and memory requests to and from the local DIMM
and for forwarding requests to other DIMMs on the memory
channel. Fully Buffered DIMM provides a high memory
bandwidth, large capacity channel solution that has a narrow
host interface. The maximum memory capacity is 288 DDR2
SDRAM devices per channel or 8 DIMMs.
This document describes the electrical and mechanical
features of a 240-pin,PC2-5300F, ECC type, Fully Buffered
Double-Data-Rate Two Synchronous DRAM Dual In-Line
Memory Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered
DIMMs use commodity DRAMs isolated from the memory
channel behind a buffer on the DIMM. They are intended for
use as main memory when installed in systems such as
servers and workstations. PC2-5300F, refers to the DIMM
naming convention indicating the DDR2 SDRAMs running at
333, MHz clock speed and offering 5300, MB/s peak
bandwidth. FB-DIMM features a novel architecture including
the Advanced Memory Buffer. This single chip component,
located in the center of each DIMM, acts as a repeater and
buffer for all signals and commands which are exchanged
between the host controller and the DDR2 SDRAMs including
data in- and output. The AMB communicates with the host
Rev.1.20, 2007-10-19
03202007-06NE-DYYI
4
Internet Data Sheet
HYS72T512420EFA–[25F/3S]–C
Fully-Buffered DDR2 SDRAM Modules
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2-6400
HYS72T512420EFA–25F–C
PC2-5300
HYS72T512420EFA–3S–C
4GB 2R×4 PC2–5300F–555–11–ZZ
2 Ranks, ECC
1Gbit (×4)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400F–555–11–H0" where 6400F
means Fully-Buffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–11" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.1 and produced
on the Raw Card "H".
Compliance Code
2)
4GB 2R×4 PC2–6400F–555–11–ZZ
Description
2 Ranks, ECC
SDRAM Technology
1Gbit (×4)
TABLE 3
Address Format
DIMM
Density
4GB
Module
Organization
512M
×
72
Memory
Ranks
2
ECC/
Non-ECC
ECC
# of SDRAMs # of row/bank/column
bits
36
14/3/11
Raw
Card
Z
TABLE 4
Components on Modules
Product Type
1)2)
HYS72T512420EFA
DRAM Components
1)
HYB18T1G400CF
DRAM Density
1Gbit
DRAM Organisation
256M
×
4
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev.1.20, 2007-10-19
03202007-06NE-DYYI
5
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