TDA7500A
DIGITAL AM/FM SIGNAL PROCESSOR
s
s
s
s
s
s
s
s
s
s
s
s
s
-
et
l
)
(s
so
b
ct
u
d
-O
ro
s)
P
t(
te
uc
le
o
od
r
s
P
b
O
te
le
so
b
O
BLOCK DIAGRAM
analog in
Σ∆
Σ∆
Σ∆
Σ∆
ADC-ref
FULL SOFTWARE FLEXIBILITY WITH TWO
24X24 BIT DSP CORES
SOFTWARE AM/FM, AUDIO AND SOUND-
PROCESSING
HARDWARE RDS FILTER, DEMODULATOR
& DECODER
INTEGRATED CODEC (4ADCs, 6DACs)
IIC AND SPI CONTROL INTERFACES
SPI DEDICATED TO DISPLAY MICRO
6 CHANNEL SERIAL AUDIO INTERFACE
(SAI)
SPDIF RECEIVER WITH SAMPLE RATE
CONVERTER
EXTERNAL MEMORY INTERFACE (EMI)
DOUBLE DEBUG INTERFACE
ON-CHIP PLL
5V-TOLERANT 3V I/O INTERFACE
12x2 MULTIFUNCTION GENERAL PURPOSE
I/O PORTS
TQFP100 (with slug down)
ORDERING NUMBER: TDA7500A
DESCRIPTION
b
O
The TDA7500A is an integrated circuit implementing
a fully digital, integrated and advanced solution to
perform the signal processing in front of the power
amplifier and behind the AM/FM tuner or any other
audio source. The chip integrates two 45 MIPs DSP
cores: one for stereo decoding, noise blanking, weak
signal processing and multipath detection and one for
sound processing, Dolby B, echo and noise cancel-
ling for the telephone.
so
te
le
ro
P
uc
d
s)
t(
P
e
od
r
s)
t(
uc
analog audio out
Decimation
Filter
Decimation
Filter
PLL Clock
Generator
SC
Filter
SC
Filter
SC
Filter
SC
Filter
SC
Filter
SC
Filter
DAC-ref
Noise
Shaper
Noise
Shaper
Noise
Shaper
ADCVDD
ADCGND
AVDD
AGND
Oversampl. Oversampl. Oversampl.
Filter
Filter
Filter
Grp & blk
sync., error
correction
IIC / SPI 1
SPI 2
SAI Transmitter
SRAM 4Mx8
DRAM 128kx4
RDS
Filter
Demod.
SPI
CLK in
Error corr. RDS blocks
or RDS clk, dat, qual
RDS
RDS bit/blk Int.
4
RDS SPI
Crystal
Oscillator
4
4
3
2
8+3
17
6 Ch. Audio Bus
2
receive bit&word clk
digital audio in
10 word SPI 1
receive stack
λ
P control
Display
λ
P
6 Channel
Audio Bus
SPDIF audio in
SAI 6ch.
Receiver
SPDIF 2ch.
Interface
2ch Sample
Rate
Converter
External Memory Interface
DSP1 Orpheus Core
including 12 GPIO´s
DSP0 Orpheus Core
X Ram 1024
Y Ram 1024
P Ram 2048
P Rom 256
Xchg
Interf.
including 12 GPIO´s
Int
Reset
4
4
2
Test
4
VDD
GND
Dolby B
FM processing,
AM processing,
Traffic memorization
4
Debug Interface
X Ram 1024
Y Ram 1024
P Ram 5632
P Rom 512
Audio processing,
Sound processing,
Noise & Echo Canc.
Debug Interface
December 2001
1/40
TDA7500A
DESCRIPTION
(continued)
An I
2
C/SPI interface is implemented for control and communication with the main micro. A separate SPI is avail-
able to interface the display micro.The DSP cores are integrated with their associated data and program mem-
ories. The peripherals and interfaces I
2
C, SPI, Serial Audio Interface (SAI), PLL Oscillator, External Memory
Interface, (EMI), General Purpose I/O register (Port A) and the D/A registers are connected to and controlled by
DSP0, whereas the A/D registers, the SPDIF and the General Purpose I/O register (Port B) are connected to
and controlled by DSP1. An hardware RDS filter , demodulator and decoder block is also embedded. No support
is needed from the DSPs but at initialisation so that RDS can work in background and in parallel with other DSP
processing. Separated Debug and Test Interfaces are connected to both DSP cores.
The TDA7500A is supposed to be used in kit with the TDA7501 or any other device of the same family. Thanks
to the serial audio interface also digital sources can be processed and a direct output to a digital bus is also
available.
The flexibility allowed by the wide memory space and by the two powerfull DSP cores make the TDA7500A us-
able for different applications. In example, inside the main radio as an audio co-processor or to perform the sig-
nal processing and equalisation associated to a digital power amplifier.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
CC
V
aio
Power supplies
Parameter
Digital
Analog
te
le
od
o
r
s
P
b
O
te
le
)-
(s
so
b
ct
u
d
-O
ro
s)
P
t(
te
uc
le
o
od
r
s
P
b
O
te
le
so
b
O
Analog Input and Output Voltage
Digital Input and Output Voltage
V
dio
V
di5
T
j
Digital Input Voltage (5V tolerant)
-0.5 to 6.5
Operating Junction Temperature Range
Storage Temperature
-40 to 125
T
stg
-55 to 150
ro
P
uc
d
s)
t(
V
V
Value
-0.5 to +4.6
-0.5 to +4.6
s)
t(
uc
V
V
V
°C
°C
Unit
-0.5 to (V
CC
+0.5)
-0.5 to (V
DD
+0.5)
Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.
THERMAL DATA
Symbol
R
th j-amb
Parameter
Value
45
20
5
Unit
°C/W
°C/W
°C/W
Thermal resistance junction to ambient
(1)
Thermal resistance junction to ambient
(2)
R
th j-case
Thermal junction to case
(3)
Note: 1. In still air
2. On 4 layers board with soldered slug
3. Measured on top side of the package
2/40
TDA7500A
PIN DESCRIPTION
N°
1
2
3
GND1
VDD1
TESTEN
I
Name
Type
Description
Ground pin dedicated to the digital circuitry.
Supply pin dedicated to the digital circuitry.
Test Enable (Input). When low, puts the chip into test mode and
muxes the XTI clock to all flip-flops. When TEST_SE is also
active, the scan chain shifting is enabled. To be connected to
Vdd in operating mode.
SCAN Enable (Input). When high with TESTEN also active,
controls the shifting of the internal scan chains. When active with
TESTEN not active, sets all tri-state outputs into hi-impedance
mode. To be connected to GND in operating mode.
System Reset (Input). A low level applied to NRESET input
initializes the IC.
4
TESTSE
I
5
6
NRESET
SCKM/DSP0_GPIO0
I
I/O
I
2
C Serial Clock Line (Input/Output)/SPI Bit Clock (Input)/
General Purpose I/O (Input/Output). Clock line for I
2
C bus. If SPI
interface is enabled, behaves as SPI bit clock. Optionally it can
be used as general purpose I/O controlled by DSP0.
I
2
C
Serial Data Line (Input/Output)/SPI Master Input Slave
Output Serial Data (Input/Output)/General Purpose I/O (Input/
Output). Data line for I
2
C bus. If SPI is enabled, behaves as
Serial Data Input when in SPI Master Mode and Serial Data
Output when in SPI Slave Mode. Optionally it can be used as
general purpose I/O controlled by DSP0.
7
MISOM/DSP0_GPIO1
I/O
-
et
l
)
(s
so
b
ct
u
d
-O
ro
s)
P
t(
te
uc
le
o
od
r
s
P
b
O
te
le
so
b
O
8
MOSIM/DSP0_GPIO2
I/O
9
SSM/DSP0_GPIO3
I
10
SCKD/DSP0_GPIO4
I
11
MISOD/DSP0_GPIO5
I/O
12
MISOD/DSP0_GPIO6
I/O
13
SSD/DSP0_GPIO7
I
b
O
so
te
le
ro
P
uc
d
s)
t(
P
e
od
r
s)
t(
uc
SPI Master Output Slave Input Serial Data (Input/Output)/
General Purpose I/O (Input/Output). Serial Data Output when in
SPI Master Mode and Serial Data Input when in SPI Slave
Mode. Optionally it can be used as general purpose I/O
controlled by DSP0.
SPI Slave Select (Input)/General Purpose I/O (Input/Output). If
SPI is enabled, behaves as Slave Select line for SPI bus.
Optionally it can be used as general purpose I/O controlled by
DSP0.
SPI Bit Clock (Input)/General Purpose I/O (Input/Output). SPI bit
clock. Optionally it can be used as general purpose I/O
controlled by DSP0.
SPI Master Input Slave Output Serial Data (Input/Output)/
General Purpose I/O (Input/Output). Behaves as Serial Data
Input when in SPI Master Mode and Serial Data Output when in
SPI Slave Mode. Optionally it can be used as general purpose I/
O controlled by DSP0.
SPI Master Output Slave Input Serial Data (Input/Output)/
General Purpose I/O (Input/Output). Serial Data Output when in
SPI Master Mode and Serial Data Input when in SPI Slave
Mode. Optionally it can be used as general purpose I/O
controlled by DSP0.
SPI Slave Select (Input)/General Purpose I/O (Input/Output).
Behaves as Slave Select line for SPI bus. Optionally it can be
used as general purpose I/O controlled by DSP0.
3/40
TDA7500A
PIN DESCRIPTION
(continued)
N°
14
15
16
17
18
19
CLKIN
AVDD
XTI
XTO
AGND
RDSINT/DSP1_GPIO4
O
I
O
Name
Type
I
Description
Clock Input pin (Input). Clock from external digital audio source
to synchronize the internal PLL.
Supply pin dedicated to the PLL.
Crystal Oscillator Input (Input). External Clock Input or crystal
Oscillator input.
Crystal Oscillator Output (Output). Crystal Oscillator output
drive.
Ground pin dedicated to the PLL.
RDS bit/block interrupt (Output)/General Purpose I/O (Input/
Output). Provides an interrupt to the main micro. Optionally it
can be used as general purpose I/O controlled by DSP1.
20
RDSARI_SCK/DSP1_GPIO3
O
SPI Bit Clock (Input)/ARI indicator (Output)/General Purpose I/O
(Input/Output). If SPI interface is enabled, behaves as SPI bit
clock. Optionally it provides the ARI indication bit. Optionally it
can be used as general purpose I/O controlled by DSP1.
SPI Slave Output Serial Data (Output)/RDS Bit Quality (Output)/
General Purpose I/O (Input/Output). If SPI is enabled, behaves
as Serial Data Output. Optionally it provides the RDS serial data
quality information. Optionally it can be used as general purpose
I/O controlled by DSP1.
SPI Slave Input Serial Data (Input)/RDS Bit Data (Output)/
General Purpose I/O (Input/Output). If SPI is enabled, behaves
as Serial Data Input. Optionally it provides the RDS serial data
stream. Optionally it can be used as general purpose I/O
controlled by DSP1.
SPI Chip Select (Input)/RDS Bit Clock (Output)/General
Purpose I/O (Input/Output). If SPI is enabled, behaves as Chip
Select line for SPI bus. Optionally it provides the 1187.5Hz RDS
Bit Clock. Optionally it can be used as general purpose I/O
controlled by DSP1.
External interrupt line (Input). When this line is asserted low, the
DSP may be interrupted. Acts as IRQA line of DSP0 core.
Ground pin dedicated to the digital circuitry.
21
RDSQAL_SO/DSP1_GPIO2
O
-
et
l
)
(s
so
b
ct
u
d
-O
ro
s)
P
t(
te
uc
le
o
od
r
s
P
b
O
te
le
so
b
O
22
RDSDAT_SI/DSP1_GPIO1
I
23
RDSCLK_SS/DSP1_GPIO0
I
24
25
26
27
28
29
30
INT
I
CGND1
CVDD1
SCRCCD
SCRMD
I
I
DSRA<7>
DSRA<6>
I/O
I/O
b
O
so
te
le
ro
P
uc
d
s)
t(
P
e
od
r
s)
t(
uc
Supply pin dedicated to the digital circuitry.
SPDIF Input 1 (Input). Stereo SPDIF input to connect a digital
audio source like a CD.
SPDIF Input 2 (Input). Stereo SPDIF input to connect a digital
audio source like a MD.
DSP SRAM Data Lines<7> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 7.
DSP SRAM Data Lines<6> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 6.
4/40
TDA7500A
PIN DESCRIPTION
(continued)
N°
31
32
33
DSRA<5>
DSRA<4>
DSRA<3>
Name
Type
I/O
I/O
I/O
Description
DSP SRAM Data Lines<5> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 5.
DSP SRAM Data Lines<4> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 4.
DSP SRAM Data Lines<3> (Input/Output)/DSP DRAM Data
Line<3>(Input/Output). This pin act as the EMI data line 3 in
both SRAM Mode and DRAM Mode.
DSP SRAM Data Lines<2> (Input/Output)/DSP DRAM Data
Line<2>(Input/Output). This pin act as the EMI data line 2 in
both SRAM Mode and DRAM Mode.
DSP SRAM Data Lines<1> (Input/Output)/DSP DRAM Data
Line<1>(Input/Output). This pin act as the EMI data line 1 in
both SRAM Mode and DRAM Mode.
DSP SRAM Data Lines<0> (Input/Output)/DSP DRAM Data
Line<0>(Input/Output). This pin act as the EMI data line 0 in
both SRAM Mode and DRAM Mode.
34
DSRA<2>
I/O
35
DSRA<1>
I/O
36
DSRA<0>
I/O
37
SRA<0>
O
DSP SRAM Address Line<0> (Output)/DSP DRAM Address
Line<0> (Output). This pin acts as the EMI address line 0 in both
SRAM Mode and DRAM Mode
DSP SRAM Address Line<1> (Output)/DSP DRAM Address
Line<1> (Output). This pin acts as the EMI address line 1 in both
SRAM Mode and DRAM Mode
DSP SRAM Address Line<2> (Output)/DSP DRAM Address
Line<2> (Output). This pin acts as the EMI address line 2 in both
SRAM Mode and DRAM Mode
DSP SRAM Address Line<3> (Output)/DSP DRAM Address
Line<3> (Output). This pin acts as the EMI address line 3 in both
SRAM Mode and DRAM Mode
DSP SRAM Address Line<4> (Output)/DSP DRAM Address
Line<4> (Output). This pin acts as the EMI address line 4 in both
SRAM Mode and DRAM Mode
DSP SRAM Address Line<5> (Output)/DSP DRAM Address
Line<5> (Output). This pin acts as the EMI address line 5 in both
SRAM Mode and DRAM Mode
DSP SRAM Address Line<6> (Output)/DSP DRAM Address
Line<6> (Output). This pin acts as the EMI address line 6 in both
SRAM Mode and DRAM Mode
DSP SRAM Address Line<7> (Output)/DSP DRAM Address
Line<7> (Output). This pin acts as the EMI address line 7 in both
SRAM Mode and DRAM Mode
DSP SRAM Address Line<8> (Output)/DSP DRAM Address
Line<8> (Output). This pin acts as the EMI address line 8 in both
SRAM Mode and DRAM Mode
-
et
l
)
(s
so
b
ct
u
d
-O
ro
s)
P
t(
te
uc
le
o
od
r
s
P
b
O
te
le
so
b
O
38
SRA<1>
O
39
SRA<2>
O
40
SRA<3>
O
41
SRA<4>
O
42
SRA<5>
O
43
SRA<6>
O
44
SRA<7>
O
45
SRA<8>
O
b
O
so
te
le
ro
P
uc
d
s)
t(
P
e
od
r
s)
t(
uc
5/40
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
