32bit TX System RISC
TX19A Family
TMP19A43CD/CZXBG
Rev2.0
2007.Aug.31
TMP19A43
32-bit RISC Microprocessor - TX19 Family
TMP19A43CZXBG, CDXBG
TMP19A43FZXBG, FDXBG
1.
Overview and Features
The TX19 family is a high-performance 32-bit RISC processor series that TOSHIBA originally developed by
integrating the MIPS16
TM
ASE (Application Specific Extension), which is an extended instruction set of high code
efficiency.
TMP19A43 is a 32-bit RISC microprocessor with a TX19A processor core and various peripheral functions
integrated into one package. It can operate at low voltage with low power consumption.
Features of TMP19A43 are as follows:
RESTRICTIONS ON PRODUCT USE
070122EBP
•
The information contained herein is subject to change without notice.
021023_D
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making
a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA
products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set
forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions
set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.
021023_A
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer,
personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These
TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality
and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”).
Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety
devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own
risk.
021023_B
•
The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q
•
The information contained herein is presented only as a guide for the applications of our products. No responsibility is
assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use.
No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.
070122_C
•
The products described in this document are subject to foreign exchange and foreign trade control laws.
060925_E
•
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter
entitled Quality and Reliability Assurance/Handling Precautions.
030619_S
TMP19A43 (rev2.0) 1-1
Overview and Features
TMP19A43
(1) TX19A processor core
1)
Improved code efficiency and operating performance have been realized through the use of two ISA
(Instruction Set Architecture) modes - 16- and 32-bit ISA modes.
•
•
2)
The 16-bit ISA mode instructions are compatible with the
MIPS16
TM
ASE
instructions of superior
code efficiency at the object level.
The 32-bit ISA mode instructions are compatible with the TX39 instructions of superior operating
performance at the object level.
Both high performance and low power dissipation have been achieved.
High performance
•
•
•
•
•
•
•
Almost all instructions can be executed with one clock.
High performance is possible via a three-operand operation instruction.
5-stage pipeline
Built-in high-speed memory
DSP function: A 32-bit multiplication and accumulation operation can be executed with one clock.
Optimized design using a low power dissipation library
Standby function that stops the operation of the processor core
Independency of the entry address
Automatic generation of factor-specific vector addresses
Automatic update of interrupt mask levels
Product name
TMP19A43CZXBG
TMP19A43CDXBG
TMP19A43FZXBG
TMP19A43FDXBG
Built-in ROM
384Kbyte
512Kbyte
384Kbyte (Flash)
512Kbyte (Flash)
Built-in RAM
20Kbyte
24Kbyte
20Kbyte
24Kbyte
Low power dissipation
3)
High-speed interrupt response suitable for real-time control
•
•
•
(2) Internal program memory and data memory
•
•
•
ROM correction function: 1 word
×
8 blocks, 8 words
×
4 blocks
Expandable to 16 megabytes (for both programs and data)
External data bus:
Separate bus/multiplexed bus
Chip select/wait controller
Activated by an interrupt or software
Data to be transferred to internal memory, internal I/O, external memory, and external I/O
: 16 channels
16-bit interval timer mode
16-bit event counter mode
16-bit PPG output (every 4 channels, synchronous outputs are possible)
Input capture function
2-phase pulse input counter function (4 channels assigned to perform this function): Multiplication-
by-4 mode
: Coexistence of 8- and 16-bit widths is possible.
: 4 channels
: 8 channels (2 interrupt factors)
(3) External memory expansion
(4) DMA controller
•
•
•
•
•
•
•
(5) 16-bit timer
TMP19A43 (rev2.0) 1-2
Overview and Features
TMP19A43
(6) 32-bit timer
•
•
•
32-bit input capture register
32-bit compare register
32-bit time base timer
: 4 channels
: 8 channels
: 1 channel
: 1 channel
: 3 channels
: 3 channels
(7) Clock timer
(8) General-purpose serial interface
•
•
(9) High-speed serial interface
Selectable between the UART mode and the synchronization mode
Selectable between the UART mode and the high-speed synchronization mode (maximum speed:
10 Mbps in the high-speed synchronization mode @40MHz)
: 1 channel
: 16 channels
Selectable between the I
2
C bus mode and the clock synchronization mode
Start by an external trigger, and the internal timer activated by a trigger
Fixed channel/scan mode
Single/repeat mode
Top-priority conversion mode
Timer monitor function
Conversion time 1.15
µsec(@
40MHz)
: 2 channels
: 1 channel
(10) Serial bus interface
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•
•
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•
(11) 10-bit A/D converter (with S/H)
(12) 8-bit D/A converter
(13) Watchdog timer
(14) Interrupt function
•
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CPU: 2 factors ...................software interrupt instruction
Internal: 46 factors.............The order of precedence can be set over 7 levels
(except the watchdog timer interrupt).
External: 48 factors ..........The order of precedence can be set over 7 levels.
Because 32 factors are associated with KWUP, the number of interrupt
factors is one.
(15) Input and output ports ...............143 terminals
(16) Standby function
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Three standby modes (IDLE, SLEEP, STOP)
Built-in PLL (multiplication by 4)
Clock gear function: The high-speed clock can be divided into 3/4, 1/2, 1/4 or 1/8.
Sub-clock: SLOW and SLEEP modes (32.768 kHz)
(17) Clock generator
(18) Endian: Bi-endian (big-endian/little-endian)
(19) Maximum operating frequency
•
•
•
•
40 MHz (PLL multiplication)
Core:
I/O and ADC:
DAC:
1.35 V to 1.65 V
2.7 V to 3.6 V
2.3 V to 2.7 V
(20) Operating voltage range
(21) Package
P-FBGA193 (12 mm
×
12 mm, 0.65 mm pitch)
TMP19A43 (rev2.0) 1-3
Overview and Features
TMP19A43
TX19 Processor Core
TX19A CPU
MAC
512K/384byte
Flash/MASK
ROM correction
Clock generator
(CG)
External bus
interface
Clock timer (1ch)
EJTAG
24K/20Kbyte
RAM
DMAC
(8ch)
INTC
HSIO/UART
0 to 2 (3ch)
I/O bus interface
16-bit TMRB
0 to 15 (16ch)
32-bit TMRC
TBT (1ch)
32-bit TMRC
Input Capture
0 to 3 (4ch)
32-bit TMRC
Compare
0 to 7 (8ch)
10-bit ADC (16ch)
8-bit DAC (2ch)
PORT0
to
PORT6
(also function as
external bus I/F)
PORT7
to
PORT8
(also function to
receive ADC inputs)
PORT9
to
PORTH
(also function as
functional pins)
SIO/UART
0 to 2 (3ch)
I2C/SIO
(1ch)
WDT
KWUP
(32ch)
Fig. 1-1 TMP19A43 Block Diagram
TMP19A43 (rev2.0) 1-4
Overview and Features
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