NCP5104, NCV5104
High Voltage, Half Bridge
Driver
The NCP5104 is a High Voltage Power gate Driver providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration. It uses the bootstrap
technique to insure a proper drive of the High−side power switch.
Features
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MARKING
DIAGRAMS
1
SOIC−8
D SUFFIX
CASE 751
8
P5104
ALYW
G
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Voltage Range: up to 600 V
dV/dt Immunity
±50
V/nsec
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to V
CC
Swing on Input Pins
Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
Matched Propagation Delays between Both Channels
1 Input with Internal Fixed Dead Time (520 ns)
Under V
CC
LockOut (UVLO) for Both Channels
Pin to Pin Compatible with Industry Standards
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
PDIP−8
P SUFFIX
CASE 626
NCP5104
A
L or WL
Y or YY
W or WW
G or
G
NCP5104
AWL
YYWWG
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Typical Applications
PINOUT INFORMATION
VCC
IN
SD
GND
1
2
3
4
8
7
6
5
VBOOT
DRV_HI
BRIDGE
DRV_LO
•
Half−Bridge Power Converters
8 Pin Package
ORDERING INFORMATION
Device
NCP5104PG
NCP5104DR2G
Package
PDIP−8
(Pb−Free)
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
Shipping
†
50 Units / Rail
2500 / Tape & Reel
NCV5104DR2G
2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2015
1
June, 2015 − Rev. 7
Publication Order Number:
NCP5104/D
NCP5104, NCV5104
Vbulk
+
C1
D4
Q1
C3
GND
NCP1395
U1
8
VBOOT
Vcc
2
7
IN
DRV_HI
3
6
SD
Bridge
4
5
GND DRV_LO
1
NCP5104
GND
GND
D3
GND
U2
R1
C4
Lf
Out−
D2
Q2
C6
T1
D1
L1
+
C3
Out+
GND
Vcc
GND
Figure 1. Typical Application Resonant Converter (LLC type)
+
Vbulk
C1
D4
Q1
C3
GND
1
2
3
4
T1
U1
8
VBOOT
Vcc
7
IN
DRV_HI
6
Bridge
SD
5
GND DRV_LO
NCP5104
C4
D1
C5
L1
+
C3
Out−
D2
C6
Q2
GND
D3
GND
U2
R1
Out+
GND
Vcc
SG3526
MC34025
TL594
NCP1561
GND
GND
Figure 2. Typical Application Half Bridge Converter
VCC
VCC
UV
DETECT
PULSE
TRIGGER
LEVEL
SHIFTER
S Q
R Q
UV
DETECT
VBOOT
DRV_HI
IN
DEAD TIME
GENERATION
BRIDGE
VCC
GND
GND
SD
DELAY
DRV_LO
GND
GND
GND
Figure 3. Detailed Block Diagram
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2
NCP5104, NCV5104
PIN DESCRIPTION
Pin Name
V
CC
IN
Description
Low Side and Main Power Supply
Logic Input
MAXIMUM RATINGS
Rating
V
CC
V
CC_transient
V
BOOT
V
BRIDGE
V
BRIDGE
V
BOOT−
V
BRIDGE
V
DRV_HI
V
DRV_LO
dV
BRIDGE
/dt
V
IN
, V
SD
R
qJA
T
ST
T
J_max
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
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Á
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
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ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
SD
Logic Input for Shutdown
Ground
GND
DRV_LO
V
BOOT
Low Side Gate Drive Output
Bootstrap Power Supply
DRV_HI
High Side Gate Drive Output
BRIDGE
Bootstrap Return or High Side Floating Supply Return
Symbol
Main power supply voltage
Main transient power supply voltage:
IV
CC_max
= 5 mA during 10 ms
VHV: High Voltage BOOT Pin
VHV: High Voltage BRIDGE pin
Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO
(see characterization curves for detailed results)
VHV: Floating supply voltage
VHV: High side output voltage
Low side output voltage
Allowable output slew rate
Inputs IN & SD
ESD Capability:
− HBM model (all pins except pins 6−7−8 in 8)
− Machine model (all pins except pins 6−7−8)
Latch up capability per JEDEC JESD78
Power dissipation and Thermal characteristics
PDIP−8: Thermal Resistance, Junction−to−Air
SO−8: Thermal Resistance, Junction−to−Air
Storage Temperature Range
Maximum Operating Junction Temperature
23
−10
50
2
200
100
178
Value
Unit
V
V
V
V
V
V
V
V
V/ns
V
kV
V
−0.3 to 20
−1 to 620
−1 to 600
−0.3 to 20
V
BRIDGE
− 0.3 to
V
BOOT
+ 0.3
−0.3 to V
CC
+ 0.3
−1.0 to V
CC
+ 0.3
°C/W
−55 to +150
+150
°C
°C
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3
NCP5104, NCV5104
ELECTRICAL CHARACTERISTIC
(V
CC
= V
boot
= 15 V, V
GND
= V
bridge
, −40°C < T
J
< 125°C, Outputs loaded with 1 nF)
T
J
−40°C to 125°C
Rating
OUTPUT SECTION
Output high short circuit pulsed current V
DRV
= 0 V, PW
v
10
ms
(Note 1)
Output low short circuit pulsed current V
DRV
= Vcc, PW
v
10
ms
(Note 1)
Output resistor (Typical value @ 25°C) Source
Output resistor (Typical value @ 25°C) Sink
High level output voltage, V
BIAS
−V
DRV_XX
@ I
DRV_XX
= 20 mA
Low level output voltage V
DRV_XX
@ I
DRV_XX
= 20 mA
DYNAMIC OUTPUT SECTION
Turn−on propagation delay (Vbridge = 0 V) (Note 2)
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 3)
Shutdown propagation delay, when Shutdown is enabled
Shutdown propagation delay, when Shutdown is disabled
Output voltage rise time (from 10% to 90% @ V
CC
= 15 V) with 1 nF load
Output voltage fall time (from 90% to 10% @ V
CC
= 15 V) with 1 nF load
Propagation delay matching between the High side and the Low side
@ 25°C (Note 4)
Internal fixed dead time (Note 5)
INPUT SECTION
Low level input voltage threshold
Input pull−down resistor (V
IN
< 0.5 V)
High level input voltage threshold
Logic “1” input bias current @ V
IN
= 5 V @ 25°C
Logic “0” input bias current @ V
IN
= 0 V @ 25°C
SUPPLY SECTION
Vcc UV Start−up voltage threshold
Vcc UV Shut−down voltage threshold
Hysteresis on Vcc
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Vboot UV Shut−down voltage threshold
Hysteresis on Vboot
Leakage current on high voltage pins to GND
(V
BOOT
= V
BRIDGE
= DRV_HI = 600 V)
Consumption in active mode (Vcc = Vboot, fsw = 100 kHz and 1 nF load on
both driver outputs)
Consumption in inhibition mode (Vcc = Vboot)
Vcc current consumption in inhibition mode
Vboot current consumption in inhibition mode
Vcc_stup
Vcc_shtdwn
Vcc_hyst
Vboot_stup
Vboot_shtdwn
Vboot_shtdwn
I
HV_LEAK
ICC1
ICC2
ICC3
ICC4
8.0
7.3
0.3
8.0
7.3
0.3
−
−
−
−
−
8.9
8.2
0.7
8.9
8.2
0.7
5
4
250
200
50
9.8
9.0
−
9.8
9.0
−
40
5
400
−
−
V
V
V
V
V
V
mA
mA
mA
mA
mA
V
IN
R
IN
V
IN
I
IN+
I
IN−
−
−
2.3
−
−
−
200
−
5
−
0.8
−
−
25
2.0
V
kW
V
mA
mA
t
ON
t
OFF
t
sd_en
t
sd_dis
t
r
t
f
Dt
DT
−
−
−
−
−
−
−
400
620
100
100
620
85
35
10
520
800
170
170
800
160
75
45
650
ns
ns
ns
ns
ns
ns
ns
ns
I
DRVsource
I
DRVsink
R
OH
R
OL
V
DRV_H
V
DRV_L
−
−
−
−
−
−
250
500
30
10
0.7
0.2
−
−
60
20
1.6
0.6
mA
mA
W
W
V
V
Symbol
Min
Typ
Max
Units
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Parameter guaranteed by design.
2. T
ON
= T
OFF
+ DT
3. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design.
4. See characterization curve for
Dt
parameters variation on the full range temperature.
5. Timing diagram definition see: Figure 4, Figure 5 and Figure 6.
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4
NCP5104, NCV5104
IN
SD
DRV_HI
DRV_LO
Figure 4. Input/Output Timing Diagram
Note: DRV_HI output is in phase with the input
IN
50%
50%
ton
Dead time
DRV_HI
toff
tf
tr
toff
tf
90%
90%
10%
10%
Dead time
tr
90%
ton
90%
DRV_LO
10%
Ton = Toff + DT
10%
Figure 5. Timing Definitions
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