Issue X-1
CM1231
Two-Channel
PicoGuard XP
TM
ESD Clamp Protection Array
Features
•
•
•
•
•
•
•
•
Two channels of ESD protection
Exceeds ESD protection to IEC61000-4-2 Level 4:
•
±12kV
contact discharge (OUT pins)
Two-stage matched clamp architecture
Matching-of-series resistor (R) of ±10mΩ typical
Flow-through routing for high-speed signal integrity
Differential channel input capacitance matching of
0.02pF typical.
Improved powered ASIC latchup protection
Dramatic improvement in ESD protection vs. best
in class single-stage diode arrays
• 40% reduction in peak clamping voltage
• 40% reduction in peak residual current
Withstands over 1000 ESD strikes*
Available in a SOT23-6 package
Product Description
The CM1231 is a member of the XtremeESD
TM
product family and is specifically designed for next
generation deep submicron ASIC protection. These
devices are ideal for protecting systems with high data
and clock rates and for circuits requiring low capacitive
loading such as USB 2.0.
The CM1231 incorporates the PicoGuard XP
TM
dual
stage ESD architecture which offers dramatically
higher system level ESD protection compared with
traditional single clamp designs. In addition, the
CM1231 provides a controlled filter roll-off for even
greater spurious EMI suppression and signal integrity.
The CM1231 protects against ESD pulses up to
±12kV
contact on the “OUT” pins per the IEC 61000-4-2
standard.
The device also features easily routed "pass-through"
differential pinouts in a 6-lead SOT23 package.
•
•
Applications
•
•
USB devices data port protection
General high-speed data line ESD protection
Electrical Schematic
V
P
V
P
CM1231
Positive Supply Rail
V
CC
A
OUT
1Ω
A
IN
Circuitry
Under
Protection
Connector
B
OUT
1Ω
B
IN
V
N
V
N
Ground Rail
*
Standard test condition is IEC61000-4-2 level 4 test circuit with each (A
OUT
/B
OUT
) pin subjected to ±12kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one
continuous test run.
© 2007 California Micro Devices Corp. All rights reserved.
12/17/07
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
1
Issue X-1
CM1231
Single and Dual Clamp ESD Protec-
tion
The following sections describe the standard single
clamp ESD protection device and the dual clamp ESD
protection architecture of the CM1231.
Single Clamp ESD Protection
Conceptually, an ESD protection device performs the
following actions upon a strike of ESD discharge into
the protected ASIC (see
Figure 1).
1. When an ESD potential is applied to the system
under test (contact or air-discharge), Kirchoff’s
Current Law (KCL) dictates that the Electrical
Overstress (EOS) currents will immediately divide
throughout the circuit, based on the dynamic
impedance of each path.
2. Ideally, the classic shunt ESD clamp will switch
within 1ns to a low-impedance path and return the
majority of the EOS current to the chassis shield/
reference ground. In actuality, if the ESD compo-
nent's response time (t
CLAMP
) is slower than the
ASIC it is protecting, or if the Dynamic Resistance
(R
DYN
) is not significantly lower than the ASIC's I/O
cell circuitry, then the ASIC will have to absorb a
large amount of the EOS energy, and may be more
likely to fail.
3. Subsequent to the ESD/EOS event, both devices
must immediately return to their original specifica-
tions, ready for an additional strike. Any deteriora-
tion in parasitics or clamping capability should be
considered a failure, as it can affect signal integrity
or subsequent protection capability (this is known
as "multi-strike" capability.)
ESD Strike
ESD
ESD
Protection
PROTECTION
Device
DEVICE
I /O
Connector
ASIC
I
SHUNT
I
RESIDUAL
Figure 1. Single Clamp ESD Protection Block Diagram
Dual Clamp ESD Protection
In the CM1231 dual clamp
PicoGuard XP
TM
architecture, the first stage begins clamping
immediately, as it does in the single clamp case. The
dramatically reduced I
RES
current from stage one
passes through the 1Ω series element and then
gradually feeds into the stage two ESD device (see
Figure 2).
The series inductive and resistive elements
further limit the current into the second stage, and
greatly attenuate the resultant peak incident pulse
presented at the ASIC side of the device.
This disconnection between the outside node and the
inside ASIC node allows the stage one clamps to turn
on and remain in the shunt mode before the ASIC
begins to shunt the reduced residual pulse. This gives
the advantage to the ESD component in the current
division equation, and dramatically reduces the
residual energy that the ASIC must dissipate.
© 2007 California Micro Devices Corp. All rights reserved.
I/O
Connector
ESD Strike
1Ω
ESD
Protection
Stage 1
ESD
Protection
Stage 2
ASIC
ASIC
DUT
I
SHUNT1
I
SHUNT2
I
RESIDUAL
Figure 2. Dual Clamp ESD Protection Block
Diagram
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
12/17/07
Issue X-1
CM1231
CM1231 Architecture Overview
The PicoGuard XP
TM
two-stage per channel matched
clamp architecture with isolated clamp rails features a
series element to radically reduce the residual ESD
current (I
RES
) that enters the ASIC under protection
(see
Figure 3).
From stage 1 to stage 2, the signal lines
go through matched dual 1
Ω
resistors.
The function of the series element (dual 1
Ω
resistors
for the CM1231) is to optimize the operation of the
stage two diodes to reduce the final I
RES
current to a
minimum while maintaining an acceptable insertion
impedance that is negligible for the associated
signaling levels.
Each stage consists of a traditional low-cap Dual Rail
Clamp structure which steer the positive or negative
ESD current pulse to either the positive (V
P
) or
negative (V
N
) supply rail.
A zener diode is embedded between V
P
and V
N
,
offering two advantages. First, it protects the V
CC
rail
against ESD strikes. Second, it eliminates the need for
an additional bypass capacitor to shunt the positive
ESD strikes to ground.
The CM1231 therefore replaces as many as 7 discrete
components, while taking advantage of precision
internal component matching for improved signal
integrity, which is not otherwise possible with discrete
components at the system level.
Advantages of the CM1231 Dual
Stage ESD Protection Architecture
Figure 4
illustrates a single stage ESD protection
device. The inductor element represents the parasitic
inductance arising from the bond wire and the PCB
trace leading to the ESD protection diodes.
Connector
ASIC
Bond Wire
Inductance
ESD
Stage
Figure 4. Single Stage ESD Protection Model
Figure 5
illustrates one of the two CM1231 channels.
Similarly, the inductor elements represent the parasitic
inductance arising from the bond wire and PCB traces
leading to the ESD protection diodes as well.
V
P
Positive Supply Rail
V
CC
Bond Wire
Inductance
Series
Element
Bond Wire
Inductance
Connector
ASIC
1Ω
I
ESD
I
RESIDUAL
Circuitry
Under
Protection
1
st
Stage
2
nd
Stage
V
N
Ground Rail
Figure 3. CM1231 Block Diagram (I
ESD
Flow During
a Positive Strike)
© 2007 California Micro Devices Corp. All rights reserved.
12/17/07
Figure 5. CM1231 Dual Stage ESD Protection
Model
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
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●
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●
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3
Issue X-1
CM1231
CM1231 Inductor Elements
In the CM1231 dual stage
PicoGuard XP
TM
architecture, the inductor elements and ESD protection
diodes interact differently compared to the single stage
model.
In the single stage model, the inductive element
presents high impedance at high frequency, i.e. during
an ESD strike. The impedance increases the
resistance of the conduction path leading to the ESD
protection element. This limits the speed that the ESD
pulse can discharge through the single stage
protection element.
In the
PicoGuard XP
TM
architecture, the inductance
elements are in series to the conduction path leading
to the protected device. The elements actually help to
limit the current and voltage striking the protected
device.
The reactance of the series and the inductor elements
in the second stage forces more of the ESD strike
current to be shunted through the first stage. At the
same time the voltage drop across series element
helps to lower the clamping voltage at the protected
terminal.
The inductor elements also tune the impedance of the
stage by cancelling the capacitive load presented by
the ESD diodes to the signal line. This improves the
signal integrity and makes the ESD protection stages
more transparent to the high bandwidth data signals
passing through the channel.
The innovative
PicoGuard XP
architecture turns the
disadvantages of the parasitic inductive elements into
useful components that help to limit the ESD current
strike to the protected device and also improves the
signal integrity of the system by balancing the
capacitive loading effects of the ESD diodes.
Graphical Comparison and Test Setup
The following graphs (see
Figure 6, Figure 7,
and
Figure 8)
show that the CM1231 (dual stage ESD protector) low-
ers the peak voltage and clamping voltage by 40% across a wide range of loading conditions in comparison to a
standard single stage device. This data was derived using the test setups shown in
Figure 9
and
Figure 10.
Normalized Vpeak
1
0.8
V oltage
V o lt a g e
1
0.8
Normalized Vclamp Initial (0-50ns)
0.6
0.4
0.2
0
0
5
10
15
RDUP(Ω)
20
25
Single Stage ESD
Device
CM1231
0.6
0.4
0.2
0
0
5
10
15
RDUP (Ω)
20
25
Single Stage ESD
Device
CM1231
Figure 6. IEC 61000-4-2 Vpeak vs.
Loading (RDUP*)
Figure 7. IEC 61000-4-2 Vclamp vs.
Loading (RDUP*)
* RDUP indicates the amount of Resistance (load) supplied to the Device Under Protection (DUP) through a vari-
able resistor.
© 2007 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
12/17/07
Issue X-1
CM1231
I
RES
12
10
Current (A)
8
6
4
2
0
0
5
10
15
RDUP(Ω)
20
25
Single Stage ESD
Device
CM1231
Figure 8. IEC 61000-4-2 I
RES
(Residual ESD Peak Current) vs. Loading (RDUP)
IEC 6100-4-2
Test Standards
Voltage
Probe
IEC 6100-4-2
Test Standards
CM1231
Device Under
Protection (DUP)
Voltage
Probe
Single Stage
ESD Device
Device Under
Protection (DUP)
R
VARIABLE
R
VARIABLE
I
RESIDUAL
I
RESIDUAL
Current
Probe
Current
Probe
Figure 9. Single Stage ESD Device Test Setup
Figure 10. CM1231 Test Setup
© 2007 California Micro Devices Corp. All rights reserved.
12/17/07
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
5
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