(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
FEATURES
Designed for PCB space savings with 2 low-power
Programmable PLLs and up to 5 clock outputs.
Low-power consumption (<10µA when PDB is
activated)
Output frequency:
o
<133MHz @ 1.8V operation
o
<166MHz @ 2.5V operation
o
<200MHz @ 3.3V operation
Input frequency:
o
Fundamental Crystal: 10MHz - 50MHz
o
Reference Input: 1MHz - 200MHz
Programmable I/O pins can be configured as Output
Enable (OE), Configuration Switching (CSEL), Power
Down (PDB) input, or Clock outputs.
Single 1.8V ~ 3.3V, ± 10% power supply
Operating temperature range from -40C to 85C
Available in GREEN/RoHS compliant SOP-8L or
MSOP-10L packages..
DESCRIPTION
The PL612-05 is an advanced dual PLL design based
on PhaseLink’s PicoPLL
TM
, world’s smallest
programmable clock, technology. This flexible
programmable architecture is ideal for high
performance, low-power, low-cost applications. When
using the power down (PDB) feature the PL612-05
consumes less than 10 µA of power, while its
Configuration Select (CSEL) function allows switching
of 2 programmable configurations. Besides its small
form factor and 3 or 5 outputs that can reduce overall
system costs, the PL612-05 offers superior phase
noise, jitter and power consumption performance.
PIN CONFIGURATION
GND
CLK4, CSEL^
CLK2, OEM^, PDB^
VDD
CLK3
1
2
3
4
5
PL612-05
10
9
8
7
6
XIN, FIN
XOUT
VDD
CLK1
CLK0
XIN, FIN
CLK2, OEM^, PDB^
VDD
CLK0
1
PL612-05
2
3
4
8
7
6
5
XOUT
VDD
CLK1
GND
MSOP-10L
^ Denotes internal pull up
SOP-8L
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/4/07 Page 1
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
PACKAGE PIN ASSIGNMENT
Name
XIN, FIN
CLK4, CSEL
CLK2, OEM,
PDB
VDD
CLK3
CLK0
GND
CLK1
XOUT
Package Pin #
Type
MSOP-10L SOP-8L
10
2
3
4, 8
5
6
1
7
9
1
-
2
3, 7
-
4
5
6
8
I
B*
B*
P
O
B*
P
O
O
Description
Crystal or Reference Clock input
- Programmable Clock (CLK4) output or
- Configuration Switching input
- Programmable Clock (CLK2) output, or
- Output Enable Master (OEM) for all clock outputs, or
- Power Down mode (PDB) input
VDD connection
Programmable Clock (CLK3) output
Programmable Clock (CLK0) output
GND connection
Programmable Clock (CLK1) output
Crystal output pin. Do Not Connect when using FIN
* Note:
All bidirectional buffers (I/Os) incorporate an internal 60KΩ
pull up resistor except when PDB mode is used. In
configurations that use PDB, the PDB pin will have a 10MΩ
pull up resistor.
KEY PROGRAMMING PARAMETERS
CLK[ 0:4 ]
Output Frequency
CLK[0]
F
VCO2
/ P
CLK[1]
F
VCO1
/ (P*(1,2,4,8)) or F
REF
/ (P*(1,2,4,8))
CLK[2]
F
REF
/ (P*(1,2,4,8))
CLK[3]
F
VCO2
/ (P*(1,2,4,8)) or F
REF
/ (P*(1,2,4,8))
CLK[4]
F
REF
/ P
Where F
VCO
= F
REF
* M / R
M = 11 bit
R = 8 bit
P = 5 bit (Odd/Even Divider)
Output Drive Strength
Each output has
three optional drive
strengths to choose
from. They are:
Low: 4mA
Std: 8mA (default)
High:16mA
Programmable Input/Output
Most pins are multi-function I/Os and can be
configured as:
OEM – (Master OE controlling all outputs)
CSEL – (Device Configuration Switching)
PDB – (Power Down)
CLK[0:4] – (Output)
HiZ or Active Low disabled state
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/4/07 Page 2
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
FUNCTIONAL DESCRIPTION
The PL612-05 is a highly featured, very flexible, advanced Dual PLL design for high performance, low-power
applications. Starting from a low-cost fundamental input crystal of 10MHz to 50MHz or a reference clock input of
1MHz to 200MHz, the PL612 is capable of producing 3 (SOP-8L) or 5 (MSOP-10L) distinct output frequencies of up
to 200MHz. Both PLLs are fully programmable, with a total of three Odd/Even (patent pending) ‘5-bit’ Post VCO
(P-counter) dividers with additional 1, 2, 4 or 8 ‘Post P-counter’ dividers to allow generating the most demanding
frequencies easily. The outputs can be programmed to deliver the generated frequencies from the PLLs, or the
reference input. Each bidirectional feature pin (I/O) on the PL613-05 incorporates a 60KΩ pull up resistor (10MΩ
for PDB function) and can be configured to perform various functions. Usage of various design features of these
products is mentioned in the following paragraphs.
PLL Programming
The two PLLs in PL612-05 are fully programmable.
Each PLL is equipped with an 8-bit input frequency
divider (R-Counter) and an 11-bit VCO frequency
feedback loop (M-Counter) divider. The PLL outputs
are transferred to Odd/Even (patent pending) 5-bit
post VCO dividers (P-Counter), as shown in the
above diagrams. In addition, there are three optional
(÷1, ÷2, ÷4 or ÷8) ‘post P-Counter’ dividers that can
further divide the VCO frequency. In general, the
PLL output frequency is determined by the following
formula
F
OUT
= (F
REF
*M) / (R*P).
For output calculations, please note that ‘P’ includes
the ‘P’ counter bits plus the additional optional (÷1,
÷2, ÷4 or ÷8) dividers, if used.
CLKx (Clock Outputs)
There are a maximum of 3 (SOP-8L) or 5 (MSOP-
10L) outputs available on the PL612-05. Clock output
frequencies can be configured as follows:
CLK[0]
F
VCO2
/ P
CLK[1]
F
VCO1
/ (P*(1,2,4,8)) or F
REF
/ (P*(1,2,4,8))
CLK[2]
F
REF
/ (P*(1,2,4,8))
CLK[3]
F
VCO2
/ (P*(1,2,4,8)) or F
REF
/ (P*(1,2,4,8))
CLK[4]
F
REF
/ P
Each output can be programmed with a 4mA, 8mA, or
16mA drive strength. The maximum output frequency
is 200MHz @ 3.3V, 166MHz @ 2.5V or 133MHz @
1.8V.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/4/07 Page 3
OEM (Master Output Enable)
One pin can be configured to be a single Master OE
(OEM) input pin that controls all the outputs of the
PL612-05. In addition the state of the disabled outputs
can be programmed to float (Hi Z) or to operate in the
‘Active low’ mode. The OEM Function operates on the
following logic:
OEM
OE Type
Osc PLL
Output
Pin
(Programmable)
0
1
0 (Default)
1
On
On
On
On
Hi Z
Active ‘0’
Normal Operation (Default)
Note: Typical enable time is 10ns.
Power-Down Control (PDB)
When activated, PDB ‘Disables all the PLLs, the
oscillator circuitry, counters, and all other active
circuitry. PDB activation disables all outputs and the
IC consumes <10µA of power. The PDB input
incorporates a 10MΩ pull up resistor for normal
operating condition.
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode. The logic for PDB is shown below:
PDB PDB Type
Osc PLL
Output
Pin
Program
Hi Z
0
Off
Off
(Default)
0
1
Off
Off
Active ‘0’
1
Normal Operation (Default)
Note: Typical enable time is 2ms.
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
On-The-Fly Configuration Switching (CSEL)
The PL612-05 can be programmed to allow switching
between 2 different configurations, allowing for
changes in the output frequency and other feature
changes. Many applications (i.e. video/audio) can
use the same design footprint, but allow for
configuration switching, adhering to various
standards. CSEL is used to make the switching
selection. This pin incorporates a 60kΩ
pull up
resistor for normal operating condition. The logic for
configuration switching of the programmed parts is
shown below:
CSEL
0
1
Programmed
Configuration
0
1(Default)
Note: Typical enable time is 100µs
.
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections ( looks like
ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/4/07 Page 4
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/4/07 Page 5
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