74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
Rev. 03 — 15 December 2008
Product data sheet
1. General description
The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accept
standard input signals. They are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
T+
and the negative voltage V
T−
is defined as the input
hysteresis voltage V
H
.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD 78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
3. Applications
I
Wave and pulse shaper
I
Astable multivibrator
I
Monostable multivibrator
NXP Semiconductors
74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP2G132DC
74AUP2G132GT
74AUP2G132GD
74AUP2G132GM
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
VSSOP8
XSON8
XSON8U
XQFN8U
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
×
1.95
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
SOT902-1
Type number
5. Marking
Table 2.
Marking codes
Marking code
aE2
aE2
aE2
aE2
Type number
74AUP2G132DC
74AUP2G132GT
74AUP2G132GD
74AUP2G132GM
6. Functional diagram
1A
1Y
1B
&
2A
2Y
2B
001aah880
001aah881
A
&
B
001aac532
Y
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
74AUP2G132_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 December 2008
2 of 19
NXP Semiconductors
74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
7. Pinning information
7.1 Pinning
74AUP2G132
1A
1
8
V
CC
1B
2
7
1Y
74AUP2G132
2Y
1A
1B
2Y
GND
1
2
3
4
001aaf164
3
6
2B
8
7
6
5
V
CC
1Y
2B
2A
GND
4
5
2A
001aaf165
Transparent top view
Fig 4.
Pin configuration SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT833-1 (XSON8)
74AUP2G132
terminal 1
index area
1Y
1
V
CC
8
74AUP2G132
1A
1B
2Y
GND
1
2
3
4
8
7
6
5
V
CC
7
1A
2B
1Y
2B
2A
2A
2
6
1B
3
4
5
2Y
GND
001aaf166
001aaj264
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2 (XSON8U)
Fig 7.
Pin configuration SOT902-1 (XQFN8U)
7.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
GND
1Y, 2Y
V
CC
Pin description
Pin
SOT765-1, SOT833-1 and SOT996-2
1, 5
2, 6
4
7, 3
8
SOT902-1
7, 3
6, 2
4
1, 5
8
data input
data input
ground (0 V)
data output
supply voltage
Description
74AUP2G132_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 December 2008
3 of 19
NXP Semiconductors
74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
8. Functional description
Table 4.
Input
nA
L
L
H
H
[1]
Function table
[1]
Output
nB
L
H
L
H
nY
H
H
H
L
H = HIGH voltage level; L = LOW voltage level.
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
-
−0.5
-
[1]
Max
+4.6
−50
+4.6
−50
+4.6
±20
50
−50
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
-
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
10. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
−40
Max
3.6
3.6
V
CC
3.6
+125
Unit
V
V
V
V
°C
74AUP2G132_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 December 2008
4 of 19
NXP Semiconductors
74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
°C
V
OH
HIGH-level output voltage
V
I
= V
T+
or V
T−
I
O
=
−20 µA;
V
CC
= 0.8 V to 3.6 V
I
O
=
−1.1
mA; V
CC
= 1.1 V
I
O
=
−1.7
mA; V
CC
= 1.4 V
I
O
=
−1.9
mA; V
CC
= 1.65 V
I
O
=
−2.3
mA; V
CC
= 2.3 V
I
O
=
−3.1
mA; V
CC
= 2.3 V
I
O
=
−2.7
mA; V
CC
= 3.0 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
T+
or V
T−
I
O
= 20
µA;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
I
I
OFF
∆I
OFF
I
CC
∆I
CC
C
I
C
O
V
OH
input leakage current
power-off leakage current
additional power-off
leakage current
supply current
additional supply current
input capacitance
output capacitance
HIGH-level output voltage
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
V
I
= V
CC
−
0.6 V; I
O
= 0 A;
V
CC
= 3.3 V
V
I
= GND or V
CC
; V
CC
= 0 V to 3.6 V
V
O
= GND; V
CC
= 0 V
V
I
= V
T+
or V
T−
I
O
=
−20 µA;
V
CC
= 0.8 V to 3.6 V
I
O
=
−1.1
mA; V
CC
= 1.1 V
I
O
=
−1.7
mA; V
CC
= 1.4 V
I
O
=
−1.9
mA; V
CC
= 1.65 V
I
O
=
−2.3
mA; V
CC
= 2.3 V
I
O
=
−3.1
mA; V
CC
= 2.3 V
I
O
=
−2.7
mA; V
CC
= 3.0 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
74AUP2G132_3
Conditions
Min
Typ
Max
Unit
V
CC
−
0.1
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
[1]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.1
1.7
-
-
-
-
-
-
-
-
0.1
0.3
×
V
CC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
0.5
40
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
pF
pF
0.75
×
V
CC
-
-
-
-
T
amb
=
−40 °C
to +85
°C
V
CC
−
0.1
0.7
×
V
CC
1.03
1.30
1.97
1.85
2.67
2.55
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 December 2008
5 of 19
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