74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
Rev. 1 — 8 November 2013
Product data sheet
1. General description
The 74AHC132-Q100; 74AHCT132-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC132-Q100; 74AHCT132-Q100 contains four 2-input NAND gates which accept
standard input signals. They can transform slowly changing input signals into sharply
defined, jitter free output signals. The gate switches at different points for positive-going
and negative-going signals. The difference between the positive voltage V
T+
and the
negative V
T
is defined as the hysteresis voltage V
H
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC132-Q100: CMOS level
For 74AHCT132-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Multiple package options
NXP Semiconductors
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC132D-Q100
74AHCT132D-Q100
74AHC132PW-Q100
74AHCT132PW-Q100
74AHC132BQ-Q100
74AHCT132BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP14
40 C
to +125
C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT108-1
Type number
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
SOT762-1
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
14 terminals; body 2.5
3
0.85 mm
4. Functional diagram
1A
1Y
2
1B
3
1
4
2A
2Y
6
1
2
4
&
3
5
2B
9
3A
5
3Y
8
9
10
3B
&
6
10
&
8
12
4A
4Y
12
11
13
mna408
&
11
13
4B
mna407
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
A
Y
B
mna409
Fig 3.
Logic diagram (one Schmitt trigger)
74AHC_AHCT132_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 8 November 2013
2 of 18
NXP Semiconductors
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
5. Pinning information
5.1 Pinning
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input nA
data input nB
data output nY
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output
nB
L
H
L
H
nY
H
H
H
L
74AHC_AHCT132_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 8 November 2013
3 of 18
NXP Semiconductors
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<0.5 V or V
O
> V
CC
+ 0.5 V
V
O
=0.5 V to (V
CC
+ 0.5 V)
[1]
[1]
20
20
25
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: above 70
C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 package: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 package: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Operating conditions
Conditions
Min
2.0
0
0
40
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
74AHCT132-Q100
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 4.5 V to 5.5 V
4.5
0
0
40
-
5.0
-
-
+25
-
5.5
5.5
V
CC
+125
20
V
V
V
C
ns/V
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
C
ns/V
ns/V
Symbol Parameter
74AHC132-Q100
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
74AHC_AHCT132_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 8 November 2013
4 of 18
NXP Semiconductors
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74AHC132-Q100
V
OH
HIGH-level
V
I
= V
T+
or V
T
output voltage
I
O
=
50 A;
V
CC
= 2.0 V
I
O
=
50 A;
V
CC
= 3.0 V
I
O
=
50 A;
V
CC
= 4.5 V
I
O
=
4.0
mA; V
CC
= 3.0 V
I
O
=
8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
T+
or V
T
output voltage
I
O
= 50
A;
V
CC
= 2.0 V
I
O
= 50
A;
V
CC
= 3.0 V
I
O
= 50
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
C
O
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3
4
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
-
1.9
2.9
4.4
2.48
3.80
-
-
-
-
-
-
-
-
-
2.2
3.15
3.85
-
-
0.1
0.1
0.1
0.44
0.44
1.0
20
10
-
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
-
V
V
V
V
V
V
V
V
V
V
A
A
pF
pF
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
output
capacitance
HIGH-level
V
I
= V
T+
or V
T
; V
CC
= 4.5 V
output voltage
I
O
=
50 A
I
O
=
8.0
mA
LOW-level
V
I
= V
T+
or V
T
; V
CC
= 4.5 V
output voltage
I
O
= 50
A
I
O
= 8.0 mA
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
I
= V
CC
or GND
74AHCT132-Q100
V
OH
4.4
3.94
-
-
-
-
-
4.5
-
0
-
-
-
-
-
-
0.1
0.36
0.1
2.0
1.35
4.4
3.80
-
-
-
-
-
-
-
0.1
0.44
1.0
20
1.5
4.4
3.70
-
-
-
-
-
-
-
0.1
0.55
2.0
40
1.5
V
V
V
V
A
A
mA
V
OL
I
I
I
CC
I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
additional
per input pin;
supply current V
I
= V
CC
2.1 V; other pins
at V
CC
or GND; I
O
= 0 A;
V
CC
= 4.5 V to 5.5 V
input
capacitance
output
capacitance
V
I
= V
CC
or GND
C
I
C
O
-
-
3
4
10
-
-
-
10
-
-
-
10
-
pF
pF
74AHC_AHCT132_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 8 November 2013
5 of 18
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
