74LVT2952-Q100
3.3 V Octal registered transceiver; 3-State
Rev. 1 — 23 September 2013
Product data sheet
1. General description
The 74LVT2952-Q100 is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive.
The 74LVT2952-Q100 device is an 8-bit registered transceiver. Two 8-bit back-to-back
registers store data flowing in both directions between two bidirectional buses.
If the clock enable (CExx) is LOW, data applied to the inputs is entered and stored on the
rising edge of the clock (CPxx). The data is then present at the 3-state output buffers, but
is only accessible when the output enable (OExx)) is LOW. Data flow from An inputs to Bn
outputs is the same as for Bn inputs to An outputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from
40 C
to +85
C
8-bit registered transceiver
Independent registers for A and B buses
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Output capability: +64 mA/32 mA
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
NXP Semiconductors
74LVT2952-Q100
3.3 V Octal registered transceiver; 3-State
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVT2952D-Q100
74LVT2952PW-Q100
40 C
to +85
C
40 C
to +85
C
Name
SO24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
Version
SOT137-1
Type number
TSSOP24 plastic thin shrink small outline package; 24 leads; SOT355-1
body width 4.4 mm
4. Functional diagram
11
CEAB
74LVT2952
CPAB
OEAB
10
9
DETAIL A
16
CE
CP
Q
A0
D
Q
CE
CP
D
8
B0
A1
A2
A3
A4
A5
A6
A7
CEBA
17
18
19
20
21
22
23
13
DETAIL A x 7
7
6
5
4
3
2
1
B1
B2
B3
B4
B5
B6
B7
CPBA
OEBA
14
15
aaa-008846
Fig 1.
Logic diagram
74LVT2952_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 September 2013
2 of 16
NXP Semiconductors
74LVT2952-Q100
3.3 V Octal registered transceiver; 3-State
15
16
17
18
19
20
21
22
23
13
14
9
A0
10
11
14
13
CPAB
CEAB
CPBA
CEBA
OEBA
OEAB
15
9
A1
A2
A3
A4
A5
A6
A7
11
10
16
17
18
19
B0
B1
B2
B3
B4
B5
B6
B7
20
21
22
8
7
6
5
4
3
2
1
23
EN3 (BA)
G1
1C5
EN4 (AB)
G2
2C6
3
6D
1
1
5D
4
7
6
5
4
3
2
1
aaa-008845
8
aaa-008844
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration
74LVT2952_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 September 2013
3 of 16
NXP Semiconductors
74LVT2952-Q100
3.3 V Octal registered transceiver; 3-State
5.2 Pin description
Table 2.
Symbol
B7 to B0
OEAB, OEBA
CPAB, CPBA
CEAB, CEBA
GND
A0 to A7
V
CC
Pin description
Pin
1, 2, 3, 4, 5, 6, 7, 8
9, 15
10, 14
11, 13
12
16, 17, 18, 19, 20, 21, 22, 23
24
Description
data input/output (B side)
output enable input (active LOW)
clock input
clock enable input
ground (0 V)
data input/output (A side)
supply voltage
6. Functional description
Table 3.
Inputs
An, Bn
X
L
H
[1]
Function selection
[1]
Internal
CPxx
[2]
X
CExx
[2]
H
L
L
nc
L
H
hold data
load data
load data
Operating mode
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH clock transition;
nc = no change.
[2]
xx = AB or BA.
Table 4.
Inputs
OExx
[2]
H
L
L
[1]
Function selection
[1]
Internal Q
X
L
H
An, Bn outputs
Z
L
H
Operating mode
outputs disabled
outputs enabled
outputs enabled
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
[2]
xx = AB or BA.
74LVT2952_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 September 2013
4 of 16
NXP Semiconductors
74LVT2952-Q100
3.3 V Octal registered transceiver; 3-State
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
[1][2]
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
Conditions
[3]
Min
0.5
0.5
0.5
50
50
-
64
65
-
Max
+4.6
7.0
+7
-
-
128
-
+150
+150
500
Unit
V
V
V
mA
mA
mA
mA
C
C
mW
output in OFF or HIGH state
V
I
< 0 V
V
O
< 0 V
output in LOW state
output in HIGH state
[3]
T
amb
=
40 C
to +85
C
[4]
-
Exceeding the values listed may permanently damage the device. The values are stress ratings only and functional operation of the
device at or beyond the values indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment, can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
For SO20 package: above 70
C
derate linearly with 8 mW/K.
For TSSOP20 package: above 60
C
derate linearly with 5.5 mW/K.
[2]
[3]
[4]
8. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
I
OH
I
OL
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level output current
LOW-level output current
current duty cycle
50 %; f
i
1 kHz
ambient temperature
input transition rise and fall rate
in free air
output enabled
Conditions
Min
2.7
0
-
-
-
40
-
Max
3.6
5.5
32
32
64
+85
10
Unit
V
V
mA
mA
mA
C
ns/V
74LVT2952_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 September 2013
5 of 16
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