19-3761; Rev 0; 8/05
KIT
ATION
EVALU
E
BL
AVAILA
1.8V, Dual, 12-Bit, 210Msps ADC for
Broadband Applications
MAX1219
General Description
The MAX1219 dual, monolithic, 12-bit, 210Msps analog-
to-digital converter (ADC) provides outstanding dynam-
ic performance up to a 250MHz input frequency. The
device operates with conversion rates up to 210Msps
while consuming only 800mW per channel.
At 210Msps and an input frequency of 200MHz, the
MAX1219 achieves a 79dBc spurious-free dynamic
range (SFDR) with excellent 65.5dB signal-to-noise ratio
(SNR) at 200MHz. The SNR remains flat (within 3dB) for
input tones up to 250MHz. This makes the MAX1219
ideal for wideband applications such as communications
receivers, cable head-end receivers, and power-amplifi-
er predistortion in cellular base-station transceivers.
The MAX1219 operates from a single 1.8V power sup-
ply. The analog inputs of each channel are designed
for AC-coupled, differential or single-ended operation.
The ADC also features a selectable on-chip divide-by-2
clock circuit that accepts clock frequencies as high as
420MHz and reduces the phase noise of the input
clock source. A low-voltage differential signal (LVDS)
sampling clock is recommended for best performance.
The converter’s digital outputs are LVDS compatible
and the data format can be selected to be either two’s
complement or offset binary.
The MAX1219 is available in a 100-pin TQFP package
with exposed paddle and is specified over the extend-
ed (-40°C to +85°C) temperature range. Refer to the
MAX1218 (170Msps) and the MAX1217 (125Msps)
data sheets for lower speed, pin-compatible devices.
o
210Msps Conversion Rate
o
Excellent Low-Noise Characteristics
SNR = 66.6dB at f
IN
= 100MHz
SNR = 65.5dB at f
IN
= 200MHz
o
Excellent Dynamic Range
SFDR = 81dBc at f
IN
= 100MHz
SFDR = 79dBc at f
IN
= 200MHz
o
Single 1.8V Supply
o
1.6W Power Dissipation at f
SAMPLE
= 210Msps
and f
IN
= 10MHz
o
On-Chip Track-and-Hold Amplifier
o
Internal 1.24V Bandgap Reference
o
On-Chip Selectable Divide-by-2 Clock Input
o
LVDS Digital Outputs with Data Clock Output
o
EV Kit Available (Order MAX1219EVKIT)
Features
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
C100E-6
MAX1219ECQ -40°C to +85°C 100 TQFP-EP*
*EP
= Exposed paddle.
Applications
Cable Modem Termination Systems (CMTS)
Cable Digital Return Path Transmitters
Cellular Base-Station Power-Amplifier Linearization
IF and Baseband Digitization
ATE and Instrumentation
Radar Systems
MAX1219
MAX1218
MAX1217
PART
Pin-Compatible Versions
RESOLUTION
(BITS)
12
12
12
SPEED GRADE
(Msps)
210
170
125
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.8V, Dual, 12-Bit, 210Msps ADC for
Broadband Applications
MAX1219
ABSOLUTE MAXIMUM RATINGS
AV
CC
to AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
OV
CC
to AV
CC
.......................................................-0.3V to +0.3V
OGND to AGND ....................................................-0.3V to +0.3V
CLKP, CLKN, INAP, INAN, INBP,
INBN to AGND .....................................-0.3V to (AV
CC
+ 0.3V)
CLKDIV,
T/BA, T/BB
to AGND .................-0.3V to (AV
CC
+ 0.3V)
REFA, REFADJA, REFB, REFADJB
to AGND...............................................-0.3V to (AV
CC
+ 0.3V)
DCOP, DCON, DA0P–DA11P, DA0N–DA11N,
DB0P–DB11P, DB0N–DB11N, ORAP, ORAN,
ORBP, ORBN to OGND .......................-0.3V to (OV
CC
+ 0.3V)
Current into any Pin.............................................................50mA
ESD Voltage on INAP, INAN, INBP, INBN
(Human Body Model).....................................................±750V
ESD Voltage on All Other Pins (Human Body Model)......±2000V
Continuous Power Dissipation (T
A
= +70°C)
100-Pin TQFP (derate 37mW/°C above +70°C).........2963mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(AV
CC
= OV
CC
= +1.8V, AGND = OGND = 0, f
SAMPLE
= 210MHz, differential input and differential sine-wave clock signal, 0.1µF
capacitors on REFA and REFB, internal reference, digital output differential R
L
= 100Ω, T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity (Note 2)
Differential Nonlinearity (Note 2)
Transfer Curve Offset
Offset Temperature Drift
ANALOG INPUTS (INAP, INAN, INBP, INBN)
Full-Scale Input Voltage Range
Full-Scale Range Temperature
Drift
Common-Mode Input Range
Differential Input Capacitance
Differential Input Resistance
Full-Power Analog Bandwidth
Reference Output Voltage
Reference Temperature Drift
REFADJ_ Input High Voltage
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
Minimum Sampling Rate
f
SAMPLE
f
SAMPLE
210
40
MHz
MHz
V
REFADJ_
Used to disable the internal reference
AV
CC
-
0.1
V
CM
C
IN
R
IN
FPBW
V
REF_
T
A
= +25°C, REFADJ_ = AGND
1.18
V
FSR
T
A
= +25°C (Note 2)
1375
1475
150
0.8
3
1.8
800
1.24
65
1.30
1625
mV
P-P
ppm/°C
V
pF
kΩ
MHz
V
ppm/°C
V
N
INL
DNL
V
OS
f
IN
= 10MHz
T
A
= +25°C, no missing codes
T
A
= +25°C (Note 2)
12
-2.5
-1
-3
10
±1
±0.3
+2.5
+1
+3
Bits
LSB
LSB
mV
µV/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE (REFA, REFB, REFADJA, REFADJB)
2
_______________________________________________________________________________________
1.8V, Dual, 12-Bit, 210Msps ADC for
Broadband Applications
DC ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= +1.8V, AGND = OGND = 0, f
SAMPLE
= 210MHz, differential input and differential sine-wave clock signal, 0.1µF
capacitors on REFA and REFB, internal reference, digital output differential R
L
= 100Ω, T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Clock Pulse-Width Low
Clock Pulse-Width High
Clock Duty Cycle
Aperture Delay
Aperture Jitter
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
Clock Input Common-Mode
Voltage
Clock Differential Input
Resistance
Clock Differential Input
Capacitance
V
CLKCM
R
CLK
C
CLK
T
A
= +25°C (Note 3)
(Note 3)
200
500
1.15 ±
0.25
10
±25%
3
mV
P-P
V
kΩ
pF
t
AD
t
AJ
SYMBOL
t
CL
t
CH
CONDITIONS
Figure 5 (Note 3)
Figure 5 (Note 3)
Set by clock-management circuit
Figures 5, 11
Figure 11
MIN
1.2
1.2
25 to
75
310
0.15
TYP
MAX
20.0
20.0
UNITS
ns
ns
%
ps
ps
RMS
MAX1219
DYNAMIC CHARACTERISTICS (at -1dBFS) (Note 4)
f
IN
= 10MHz
Signal-to-Noise Ratio
SNR
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 10MHz
Effective Number of Bits
ENOB
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 10MHz
Signal-to-Noise Plus Distortion
SINAD
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 10MHz
Spurious-Free Dynamic Range
SFDR
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 10MHz
Worst Harmonic
(HD2 or HD3)
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
Two-Tone Intermodulation
Distortion
f
IN1
= 29MHz at -7dBFS
f
IN2
= 31MHz at -7dBFS
f
IN1
= 97MHz at -7dBFS
f
IN2
= 100MHz at -7dBFS
72
72
64.8
64.8
10.5
10.5
65
65
67.1
66.7
66.6
65.5
10.9
10.8
10.8
10.5
67
66.6
66.3
65.2
88
83.5
81
79
-88
-84
-81
-79
87
dBc
83
-72
-72
dBc
dBc
dB
Bits
dB
TTIMD
_______________________________________________________________________________________
3
1.8V, Dual, 12-Bit, 210Msps ADC for
Broadband Applications
MAX1219
DC ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= +1.8V, AGND = OGND = 0, f
SAMPLE
= 210MHz, differential input and differential sine-wave clock signal, 0.1µF
capacitors on REFA and REFB, internal reference, digital output differential R
L
= 100Ω, T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Channel Isolation
LVCMOS LOGIC INPUTS (CLKDIV,
T/BA, T/BB)
Input High Voltage
Input Low Voltage
Input Capacitance
LVDS DIGITAL OUTPUTS (DA0P/N–DA11P/N, DB0P/N–DB11P/N, ORAP/N, ORBP/N, DCOP/N)
Differential Output Voltage
Output Offset Voltage
OUTPUT TIMING CHARACTERISTICS
CLK to Data Propagation Delay
CLK to DCO Propagation Delay
DCO to Data Propagation Delay
LVDS Output Rise Time
LVDS Output Fall Time
Output Data Pipeline Delay
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
AV
CC
OV
CC
I
AVCC
I
OVCC
P
DISS
PSRR
f
IN
= 10MHz
f
IN
= 10MHz
f
IN
= 10MHz
T
A
= +25°C (Note 5)
1.71
1.71
1.8
1.8
760
120
1.6
5
1.89
1.89
900
160
1.908
V
V
mA
mA
W
mV/V
t
PDL
t
CPDL
t
RL
t
FL
t
LATENCY
Figure 5 (Note 3)
Figure 5 (Note 3)
2.3
20% to 80%, C
L
= 5pF
20% to 80%, C
L
= 5pF
Figure 5
1.7
3.7
2.7
350
350
11
3.1
ns
ns
ns
ns
ns
Clock
Cycles
|V
OD
|
V
OS
225
1.125
490
1.310
mV
V
V
IH
V
IL
2
0.8 x
OV
CC
0.2 x
OV
CC
V
V
pF
SYMBOL
CONDITIONS
f
IN
= 200MHz, A
IN
= -1dBFS
MIN
TYP
90
MAX
UNITS
dB
CHANNEL CROSSTALK AND CHANNEL MATCHING SPECIFICATIONS
t
PDL
- t
CPDL
(Note 3)
Note 1:
Values at T
A
= +25°C to +85°C are guaranteed by production test. Values at T
A
< +25°C are guaranteed by design and
characterization.
Note 2:
Static linearity and offset parameters are computed from a best-fit straight line through the code transition points.
The full-scale range (FSR) is defined as 4095 x slope of the line.
Note 3:
Parameter guaranteed by design and characterization; T
A
= -40°C to +85°C.
Note 4:
ENOB and SINAD are computed from a curve fit.
Note 5:
PSRR is measured with the analog and output supplies connected to the same potential.
4
_______________________________________________________________________________________
1.8V, Dual, 12-Bit, 210Msps ADC for
Broadband Applications
MAX1219
Typical Operating Characteristics
(AV
CC
= OV
CC
= 1.8V, f
SAMPLE
= 210MHz, differential input and differential sine-wave clock signal, 0.1µF capacitors on REFA and
REFB, internal reference, digital output differential R
L
= 100Ω, T
A
= +25°C, unless otherwise noted.)
FFT PLOT
(16,384 SAMPLES)
MAX1219 toc01
FFT PLOT
(16,384 SAMPLES)
MAX1219 toc02
FFT PLOT
(16,384 SAMPLES)
f
IN
= 100Hz
f
SAMPLE
= 210MHz
A
IN
= -0.971dBFS
SINAD = 66.323dB
SNR = 66.576dB
THD = -78.811dBc
SFDR = 80.762dBc
HD2 = -93.597dBc
HD3 = -80.764dBc
MAX1219 toc03
0
-25
AMPLITUDE (dB)
f
IN
= 10.3Hz
f
SAMPLE
= 210MHz
A
IN
= -1dBFS
SINAD = 67.026dB
SNR = 67.129dB
THD = -83.324dBc
SFDR = 87.469dBc
HD2 = -94.214dBc
HD3 = -87.469dBc
0
-25
AMPLITUDE (dB)
-50
-50
AMPLITUDE (dB)
105
-75
-75
f
IN
= 65Hz
f
SAMPLE
= 210MHz
A
IN
= -1.041dBFS
SINAD = 66.596dB
SNR = 66.745dB
THD = -81.307dBc
SFDR = 83.358dBc
HD2 = -92.863dBc
HD3 = -84.022dBc
0
-25
-50
-75
-100
-100
-100
-125
0
21
42
63
84
ANALOG INPUT FREQUENCY (MHz)
105
-125
0
21
42
63
84
ANALOG INPUT FREQUENCY (MHz)
-125
0
21
42
63
84
ANALOG INPUT FREQUENCY (MHz)
105
FFT PLOT
(16,384 SAMPLES)
MAX1219 toc04
FFT PLOT
(16,384 SAMPLES)
MAX1219 toc05
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 210MHz, A
IN
= -1dBFS)
SNR
MAX1219 toc06
0
-25
AMPLITUDE (dB)
-50
AMPLITUDE (dB)
-50
SNR/SINAD (dB)
-75
f
IN
= 200Hz
f
SAMPLE
= 210MHz
A
IN
= -0.949dBFS
SINAD = 65.17dB
SNR = 65.5dB
THD = -76.527dBc
SFDR = 79.593dBc
HD2 = -86.659dBc
HD3 = -79.593dBc
0
-25
-75
f
IN
= 250Hz
f
SAMPLE
= 210MHz
A
IN
= -1.039dBFS
SINAD = 63.842dB
SNR = 64.779dB
THD = -70.965dBc
SFDR = 72.255dBc
HD2 = -80.836dBc
HD3 = -72.255dBc
70
68
66
64
SINAD
62
60
-100
-100
58
-125
0
21
42
63
84
ANALOG INPUT FREQUENCY (MHz)
105
-125
0
21
42
63
84
ANALOG INPUT FREQUENCY (MHz)
105
56
10
60
110
160
210
260
ANALOG INPUT FREQUENCY (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 210MHz, A
IN
= -1dBFS)
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
10
60
MAX1219 toc07
SFDR/(-THD) vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 210MHz, A
IN
= -1dBFS)
85
80
SFDR/(-THD) (dBc)
75
70
65
60
55
50
45
40
-THD
SFDR
MAX1219 toc08
90
HD3
HD2/HD3 (dBc)
HD2
110
160
210
260
10
60
110
160
210
260
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
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