TMS320C6000 FAMILY: EMIF
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
1
TMS320C6000 FAMILY: EMIF
Introduction.
Characteristics, signals, memory map, alignment.
Configuration registers.
Types of interface.
Asynchronous interface.
Introduction, waveforms.
Case Study I: Peripheral connection.
Case Study II: Memory connection.
Interface with synchronous static memories.
Synchronous static memories.
Interface description.
Example.
Interface with synchronous dynamic memories.
SDRAM memories.
Interface description.
Example.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
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Need for an EMIF
Need for
EMIF):
Traditional DSP (with no
an EMIF
Peripheral/
Memory
H/W
Interface
DSP
When interfacing a slow peripheral/memory to a fast
DSP, some hardware interface is required.
This hardware interface requires fast components in
order to keep up with the DSP.
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Need for an EMIF (II)
Need for
EMIF):
Traditional DSP (with no
an EMIF
Peripheral/
Memory
H/W
Interface
DSP
Drawback of the hardware interface:
High cost (additional components).
Power consumption.
Difficult to debug.
Cannot be upgraded.
Prone to errors.
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Sistemas Electrónicos Digitales Avanzados
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The EMIF
The EMIF
The EMIF supports a
glueless interface
to several
external devices, including:
Synchronous burst SRAM (SBSRAM).
Synchronous DRAM (SDRAM).
Asynchronous devices, including SRAM, ROM and FIFO’s.
An external shared-memory device.
For more information on different memory types see
spra631.pdf
A detailed description for each memory type interface
can be found in:
Asynchronous SRAM:
spra542a.pdf
Synchronous burst SRAM:
spra533.pdf
Synchronous DRAM:
spra433b.pdf
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The EMIF
The C621x/C671x services requests of the external bus from the
The EMIF
requestors:
On-chip Enhanced Direct Memory Access (EDMA) controller.
External shared-memory device controller.
EMIF
L1P Cache
C6000 DSP core
Instruction Fetch
Other
Peripherals
Enhanced
DMA
Controller
Instruction Dispatch
L2
Memory
Instruction Decode
Data Path A
A Register File
Interrupt
Selector
Power Down
Logic
Boot
Configuration
L1D Cache
L1
S1 M1 D1
Data Path B
B Register File
D2 M2 S2
L2
Control
Registers
Control
Logic
Test
In–Circuit
Emulation
Interrupt
Control
PLL
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6
MEMORY MAP
Byte Address
0000_0000
64K x 8 Internal
(L2 cache)
External Memory
Async
(SRAM, ROM, etc.)
Sync
(SBSRAM, SDRAM)
0180_0000
On-chip Peripherals
Internal Memory
Unified (data or prog)
prog
)
4 blocks - each can be
RAM or cache
8000_0000
9000_0000
A000_0000
B000_0000
FFFF_FFFF
0
256M x 8 External
1
256M x 8 External
2
256M x 8 External
3
256M x 8 External
Level 1 Cache
4KB Program
4KB Data
Not in map
4K
P
CPU
4K
D
L2
64K
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MEMORY MAP (II)
Description
Internal RAM (L2) mem
EMIF control regs
Cache configuration reg
L2 base addr & count regs
L1 base addr & count regs
L2 flush & clean regs
CE0 mem attribute regs
CE1 mem attribute regs
CE2 mem attribute regs
CE3 mem attribute regs
HPI control reg
McBSP0 regs
McBSP1 regs
Timer0 regs
Timer1 regs
Interrupt selector regs
EDMA parameter RAM
EDMA control regs
QDMA regs
QDMA pseudo-regs
McBSP0 data
McBSP1 data
CE0, 256 MBytes
CE1, 256 MBytes
CE2, 256 MBytes
CE3, 256 MBytes
Origin
0x00000000
0x01800000
0x01840000
0x01844000
0x01844020
0x01845000
0x01848200
0x01848240
0x01848280
0x018482c0
0x01880000
0x018c0000
0x01900000
0x01940000
0x01980000
0x019c0000
0x01a00000
0x01a0ffe0
0x02000000
0x02000020
0x30000000
0x34000000
0x80000000
0x90000000
0xA0000000
0xB0000000
Length
0x00010000
0x00000024
0x00000004
0x00000020
0x00000020
0x00000008
0x00000010
0x00000010
0x00000010
0x00000010
0x00000004
0x00000028
0x00000028
0x0000000c
0x0000000c
0x0000000c
0x00000800
0x00000020
0x00000014
0x00000014
0x04000000
0x04000000
0x10000000
0x10000000
0x10000000
0x10000000
8
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
C6211/C6711 EMIF Features
Features
Bus Width
# Memory Spaces
Addressable Space (Mbytes)
Synchronous Clocking
Width Support
Supported Memory Type at CE1
Control Signals
Synchronous memory in system
Additional registers
PDT Support
ROM/Flash
Asynchronous memory I/O
Pipeline SBSRAM
C621x / C671x
32
4
512
Independent ECLKIN
8/16/32
All types
Mixed all control signals
Both SDRAM and SBSRAM
SDEXT
No
Yes
Yes
Yes
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C6713 EMIF Signals
C6211/C6711 EMIF Signals
ECLKIN
ECLKOUT
ED[31:0]
†
EA[21:2]
CE[3:0]
BE[3:0]
Enhanced
data
memory
controller
External
memory
interface
(EMIF)
ARDY
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
AWE/SDWE/SSWE
HOLD
HOLDA
Control
registers
BUSREQ
MUXed
Asynch/SDRAM/SBSRAM
control
Shared by
all external
interfaces
Clock signals:
ECLKIN
ECLKOUT
Data bus: ED[31:0]
Address bus: EA[21:2]
Byte enable: BE[3:0]
Control signals:
Asynchronous ready.
Memory type
depending.
Bus arbitration:
Internal
peripheral bus
Hold
Hold acknowledge.
Bus request.
10
For a description of the signals see:
\Links\signals.pdf
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
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