NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Connection Diagrams
DIP PIN CONFIGURATIONS
27C280 27C240 27C220
A18
CE/PGM
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE/V
PP
Note:
DIP
NM27C210
27C220 27C240 27C280
V
CC
XX/PGM
NC
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
PGM
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
DS011093-7
XXV
PP
CE/PGM
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
XXV
PP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
XX/V
PP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C210 pins.
Commercial Temperature Range
(0
°
C to +70
°
C) V
CC
= 5V
±
10%
Parameter/Order Number
NM27C210 Q, V, N 90
NM27C210 Q, V, N 120
NM27C210 Q, V, N 150
Pin Names
A0–A15
CE
OE
O0–O15
PGM
XX
Addresses
Chip Enable
Output Enable
Outputs
Program
Don’t Care (During Read)
No Connect
Access Time (ns)
90
120
150
Industrial Temperature Range
(-40
°
C to +85
°
C) V
CC
= 5V
±
10%
Parameter/Order Number
NM27C210 QE, VE, NE 120
NM27C210 QE, VE, NE 150
Package Types: NM27C210 Q, V, N XXX
Q = Quartz-Windowed Ceramic DIP package
N = Plastic DIP package
V = PLCC package
• All packages conform to JEDEC standard.
• All versions are guaranteed to function in slower
applications.
NC
Access Time (ns)
120
150
PLCC Pin Configuration
O13
O14
O15
CE
XX/VPP
NC
VCC
XX/PGM
NC
A15
A14
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
7 6 5 4 3 2
17
4443424140
1
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
181920212223242526 2728
39
29
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
O3
O2
O1
O0
OE
NC
A1
A2
A2
A3
A4
Top View
DS011093-3
2
www.fairchildsemi.com
NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
All Input Voltages except A9 with
Respect to Ground (Note 10)
V
PP
and A9 with Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
-65°C to +150°C
All Output Voltages with
Respect to Ground (Note 10)
V
CC
+ 1.0V to GND - 0.6V
Operating Range
-0.6V to +7V
-0.6V to +14V
-0.6V to +7V
>2000V
Range
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
CC
+5V
+5V
Tolerance
±10%
±10%
DC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
I
SB2
I
CC
I
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current
(CMOS)
V
CC
Standby Current
V
CC
Active Current
V
PP
Supply Current
Input Load Current
Output Leakage Current
Test Conditions
Min
-0.5
2.0
Max
0.8
V
CC
+1
0.4
Units
V
V
V
V
I
OL
= 2.1 mA
I
OH
= -2.5 mA
CE = V
CC
±
0.3V
CE = V
IH
CE = OE = V
IL
I/O = 0 mA
V
PP
= V
CC
V
IN
= 5.5 or GND
V
OUT
= 5.5V or GND
-1
-10
f = 5 MHz
3.5
100
1
40
10
1
10
µA
mA
mA
µA
µA
µA
AC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
DF
(Note 2)
t
OH
(Note 2)
Parameter
Min
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output Float
Output Hold from Addresses,
CE or OE , Whichever
Occurred First
90
Max
90
90
50
30
120
Min
Max
120
120
50
35
150
Min
Max
150
150
50
45
Units
ns
0
0
0
Capacitance
(Note 2) T
A
= +25°C, f = 1 MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
12
13
Max
20
20
Units
pF
pF
3
www.fairchildsemi.com
NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
≤5
ns
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs
AC Waveforms
(Note 6) , (Note 7) , (Note 9)
Adresses
2.0V
0.8V
Addresses Valid
CE
2.0V
0.8V
t
CE
2.0V
0.8V
t
OE
Note 3
t
DF
Notes 4, 5
High Z
t
OH
DS011093-4
t
CF
Notes 4, 5
OE
Output
2.0V
0.8V
High Z
t
ACC
Note 3
Note 1:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE .
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
: 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
4
www.fairchildsemi.com
NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
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