NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
Connection Diagrams
DIP PIN CONFIGURATIONS
27C280 27C220 27C210
A18
CE/PGM
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE/V
PP
XXV
PP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
XXV
PP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
XX/V
PP
CE/PGM
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
DIP
NM27C240
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
27C210 27C220 27C280
V
CC
XX/PGM
NC
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
PGM
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
DS011949-2
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C240 pins.
Commercial Temperature Range
(0°C to +70°C) V
CC
= 5V
±10%
Parameter/Order Number
NM27C240 Q, V, N 100
NM27C240 Q, V, N 120
NM27C240 Q, V, N 150
Extended Temperature Range
(-40° to +85°C) V
CC
= 5V
±10%
Parameter/Order Number
NM27C240 QE, VE, NE 120
NM27C240 QE, VE, NE 150
Access Time (ns)
100
120
150
Access Time (ns)
120
150
PLCC Pin Configuration
Package types: NM27C240 Q, V, N XXX
Q = Quartz-Windowed Ceramic DIP Package
V = PLCC Package
N = Plastic DIP Package
• All packages conform to JEDEC standard.
• All versions are guaranteed to function in slower applications.
O13
O14
O15
CE/PGM
XX/VPP
NC
VCC
A17
A16
A15
A14
Note:
Surface mount PLCC package available for commercial and extended
temperature ranges only.
Pin Names
A0–A15
CE/PGM
OE
O0–O15
XX
NC
Addresses
Chip Enable/Program
Output Enable
Outputs
Don’t Care (During Read)
No Connect
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
7 6 5 4 3 2 4443424140 39
A13
1
A12
8
38
9
37
A11
10
36
A10
11
35
A9
12
34
GND
13
33
NC
14
32
A8
15
31
A7
16
30
A6
A5
181920212223242526 2728
29
17
O3
O2
O1
O0
OE
NC
A0
A1
A2
A3
A4
Top View
DS011949-3
2
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
All Input Voltages except A9 with
Respect to Ground (Note 10)
V
PP
and A9 with
Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
All Output Voltages with Respect
to Ground (Note 10)
-65°C to +150°C
-0.6V to +7V
-0.6V to +14V
-0.6V to +7V
>2000V
V
CC
+ 1.0V to GND - 0.6V
Operating Range
Range
Commercial
Industrial
Temperature
0°C to +70°C
-40V°C to +85°C
V
CC
+5V
+5V
Tolerance
±10%
±10%
DC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
I
SB2
I
CC
I
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current (CMOS)
V
CC
Standby Current (TTL)
V
CC
Active Current
V
PP
Supply Current
Input Load Current
Output Leakage Current
I
OL
= 2.1 mA
Conditions
Min
-0.5
2.0
Max
0.8
V
CC
+1
0.4
Units
V
V
V
V
I
OH
= -2.5 mA
CE = V
CC
±0.3V
CE = V
IH
CE = OE = V
IL
, I/O = 0 mA
V
PP
= V
CC
V
IN
= 5.5V or GND
V
OUT
= 5.5V or GND
f=5 MHz
3.5
100
1
40
10
-1
-10
1
10
µA
mA
mA
µA
µA
µA
AC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
DF
(Note 2)
t
OH
(Note 2)
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output Float
Output Hold from Addresses CE or
OE , Whichever Occurred First
100
Min
Max
100
100
50
35
0
120
Min
Max
120
120
50
35
0
150
Min
Max
150
150
50
45
0
Units
ns
Capacitance
T
A
= +25˚C, f = 1 MHz (Note 2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
12
13
Max
20
20
Units
pF
pF
3
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
≤5
ns
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs
AC Waveforms
(Notes 6, 7) (Note 9)
Adresses
2.0V
0.8V
Addresses Valid
CE
2.0V
0.8V
t
CE
2.0V
0.8V
t
OE
Note 3
t
DF
Notes 4, 5
High Z
t
OH
DS011949-4
t
CF
Notes 4, 5
OE
Output
2.0V
0.8V
High Z
t
ACC
Note 3
Note 1:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
–t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE .
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
: 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
4
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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM
DC Electrical Characteristics
(Notes 11, 12, 13, 14)
Symbol
t
AS
t
OES
t
DS
t
VPS
t
VCS
t
AH
t
DH
t
DF
t
PW
t
OE
I
PP
I
CC
T
A
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
OE Setup Time
Data Setup Time
V
PP
Setup Time
V
CC
Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output Float Delay
Program Pulse Width
Data Valid from OE
V
PP
Supply Current during Programming Pulse
V
CC
Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
2.4
0.8
0.8
20
6.25
12.5
5
0.0
4.0
2.0
2.0
0.45
25
6.5
12.75
CE = V
IL
CE = V
IL
, PGM = V
IL
CE = V
IL
Parameter
Address Setup Time
Conditions
Min
1
1
1
1
1
0
1
0
45
Typ
Max
Units
µs
µs
2.4
µs
µs
µs
µs
µs
60
50
105
100
30
30
30
6.75
13.0
ns
µs
ns
mA
mA
°C
V
V
ns
V
V
V
V
Programming Waveforms
(Note 13)
Program
Adresses
2.0V
0.8V
t
AS
Data
2.0V
0.8V
t
DS
V
CC
6.25V
t
VCS
Data In Stable
Add N
t
DH
High Z
Address N
t
AH
Data Out Valid
Add N
t
DF
Program Verify
V
PP
12.75V
t
VPS
CE/PGM
2.0V
0.8V
t
PW
t
OES
t
OE
OE
2.0V
0.8V
DS011949-5
Note 11:
Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a board with
voltage applied to V
PP
or V
CC
.
Note 13:
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1
µF
capacitor is required across V
PP
, V
CC
to GND to suppress spurious voltage transients
which may damage the device.
Note 14:
During power up the CE/PGM pin must be brought high (≥V
IH
) either coincident with or before power is applied to V
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