DRAM MODULE
KMM366F160(8)0BK2 EDO Mode without buffer
16M x 64 DRAM DIMM Using 16Mx4, 4K & 8K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung KMM366F160(8)0BK2 is a 16Mx64bits
Dynamic RAM high density memory module. The Samsung
KMM366F160(8)0BK2 consists of sixteen CMOS 16Mx4bits
DRAMs in SOJ 400mil packages and one 2K EEPROM for
SPD in 8-pin SOP package mounted on a 168-pin glass-
epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The
KMM366F160(8)0BK2 is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
KMM366F160(8)0BK2
FEATURES
• Part Identification
Part number
KMM366F1600BK2
KMM366F1680BK2
PKG
SOJ
SOJ
Ref.
4K
8K
CBR Ref.
ROR Ref.
4K/64ms
4K/64ms
8K/64ms
• New JEDEC standard proposal without buffer
• Serial Presence Detect with EEPROM
• Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
• LVTTL compatible inputs and outputs
• Single +3.3V±0.3V power supply
• PCB : Height(1000mil), double sided component
PIN CONFIGURATIONS
Pin Front Pin Front Pin Front Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
*CB0
*CB1
V
SS
NC
NC
V
CC
W0
CAS0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
CAS1
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
A12
V
CC
V
CC
DU
V
SS
OE2
RAS2
CAS2
CAS3
W2
V
CC
NC
NC
*CB2
*CB3
V
SS
DQ16
DQ17
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ18
DQ19
V
CC
DQ20
NC
DU
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
CC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
*CB4
*CB5
V
SS
NC
NC
V
CC
DU
CAS4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
CAS5
*RAS1
DU
V
SS
A1
A3
A5
A7
A9
A11
*A13
V
CC
DU
DU
V
SS
DU
*RAS3
CAS6
CAS7
DU
V
CC
NC
NC
*CB6
*CB7
V
SS
DQ48
DQ49
Pin Back
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ50
DQ51
V
CC
DQ52
NC
DU
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
CC
PIN NAMES
Pin Name
A0 - A11
A0 - A12
DQ0 - DQ63
W0, W2
OE0, OE2
RAS0, RAS2
CAS0 - CAS7
V
CC
V
SS
NC
DU
SDA
SCL
SA0 -SA2
*CB0 - CB7
Function
Address Input(4K ref.)
Address Input(8K ref.)
Data In/Out
Read/Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power(+3.3V)
Ground
No Connection
Don′t use
Serial Address /Data I/O
Serial Clock
Address in EEPROM
Check Bit
* These pins are not used in this module.
NOTE : A12 is used for only KMM366F1680BK2 (8K ref.)
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
KMM366F160(8)0BK2
RAS0
W0
OE0
A0-A11(A12)
CAS0
U0
RAS2
W2
OE2
CAS4
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CAS5
U2
U9
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U1
U10
CAS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U11
U3
U12
CAS2
U5
CAS6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CAS7
U7
U14
U6
U15
CAS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U16
U8
U17
NOTE : A12 is used for only KMM366F1680BK2 (8K ref.)
Serial PD
V
CC
0.1 or 0.22uF Capacitor
under each DRAM
Vss
To all DRAMs
SCL
A0
A1
A2
SDA
SA0 SA1 SA2
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
KMM366F160(8)0BK2
Rating
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
16
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3
*2
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
*1
0.8
Unit
V
V
V
V
*1 : V
CC
+1.3V at pulse width≤15ns which is measured at V
CC
.
*2 : -1.3V at pulse width≤15ns which is measured at V
SS
.
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM366F1680BK2
Min
-
-
KMM366F1600BK2
Min
-
-
-
-
-
-
-
-
-
-
-10
-5
2.4
-
Max
1920
1760
32
1920
1760
1760
1600
8
1920
1760
10
5
-
0.4
Max
1440
1280
32
1440
1280
1600
1440
8
1440
1280
10
5
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-10
-5
2.4
-
I
CC1
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
: Extended Data Out Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I(
IL)
: Input Leakage Current (Any input 0≤V
IN
≤V
CC
+0.5V, all other pins not under test=0 V)
I(
OL)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤V
CC
)
V
OH
: Output High Voltage Level (I
OH
= -2mA)
V
OL
: Output Low Voltage Level (I
OL
= 2mA)
* NOTE : I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle time,
t
HPC
.
DRAM MODULE
CAPACITANCE
(T
A
= 25°C, V
CC
=3.3V, f = 1MHz)
Item
Input capacitance[A0-A12]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0 - CAS7]
Input/Output capacitance[DQ0-DQ63]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
CDQ
Min
-
-
-
-
-
KMM366F160(8)0BK2
Max
90
66
66
24
17
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=3.3V±0.3V. See notes 1,2.)
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading C
L
=100pF
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
OE to output in Low-Z
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
Refresh period (4K & 8K Ref.)
Write command set-up time
CAS to W dealy time
RAS to W dealy time
Symbol
-5
Min
84
128
50
13
25
3
3
3
1
30
50
8
38
8
17
12
5
0
7
0
7
25
0
0
0
7
7
8
7
0
7
64
0
33
70
0
38
84
10K
37
25
10K
13
50
3
3
3
1
40
60
10
40
10
20
15
5
0
10
0
10
30
0
0
0
10
10
10
10
0
10
64
10K
45
30
10K
13
50
Max
Min
104
153
60
15
30
-6
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
7
7
7
8
8
4
9
3,4,9
3,4,5
3,9
3
3
6,10
2
Note
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
OLZ
t
CEZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CWD
t
RWD
DRAM MODULE
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=3.3V±0.3V. See notes 1,2.)
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading C
L
=100pF
Parameter
Column address to W delay time
CAS precharge to W delay time
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper page mode cycle time
Hyper page mode read-modify write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
OE to CAS hold time
CAS hold time to OE
OE precharge time
W pulse width (Hyper page cycle)
Symbol
-5
Min
45
47
5
10
5
28
20
67
7
50
30
13
10
3
5
5
3
3
15
5
5
5
5
13
13
13
200K
Max
KMM366F160(8)0BK2
-6
Min
53
58
5
10
5
35
25
73
10
60
35
15
13
3
5
5
3
3
15
5
5
5
5
13
13
13
200K
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
7
t
AWD
t
CPWD
t
CSR
t
CHR
t
RPC
t
CPA
t
HPC
t
HPRWC
t
CP
t
RASP
t
RHCP
t
OEA
t
OED
t
OEZ
t
OEH
t
DOH
t
REZ
t
WEZ
t
WED
t
OCH
t
CHO
t
OEP
t
WPE
3
11
11
6
6,10
6
FPGA/CPLD
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