Latch-Up Current .................................................... > 200 mA
Device
CYU01M16SCE
Range
Industrial
Operating
Temperature (T
A
)
–40°C to +85°C
V
CC
2.2V to
3.6V
DC Electrical Characteristics
(Over the Operating Range)
[5, 6, 7]
CYU01M16SCE-70 ns
Parameter
V
CC
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH Voltage I
OH
= –0.1 mA
V
CC
= 2.2V to 3.6V
Output LOW Voltage I
OL
= 0.1 mA
V
CC
= 2.2V to 3.6V
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply
Current
Automatic CE
Power-Down
Current—CMOS
Inputs
Automatic CE
Power-Down
Current—CMOS
Inputs
V
CC
= 2.2V to 3.6V
V
CC
= 2.2V to 3.6V
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
f = f
MAX
= 1/t
RC
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
f = 1MHz
I
SB1
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V, f = f
MAX
(Address and Data Only), f = 0
(OE, WE, BHE and BLE), V
CC
= 3.60V
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or
V
IN
< 0.2V,
f = 0, V
CC
=V
CCMAX
0.8 * V
CC
–0.3
–1
–1
18
Test Conditions
Min.
2.2
V
CC
– 0.2
0.2
V
CC
+ 0.3V
0.2 * V
CC
+1
+1
25
Typ.
[4]
3.0
Max.
3.6
Unit
V
V
V
V
V
µA
µA
mA
3
55
5
70
mA
µA
I
SB2
55
70
µA
Capacitance
[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance
[8]
Parameter
Θ
JA
Θ
JC
Description
Test Conditions
VFBGA
56
11
Unit
°C/W
°C/W
Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods
and procedures for measuring thermal
Thermal Resistance (Junction to Case)
impedence, per EIA/JESD51
Notes:
5. V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
6. V
IH(Max)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
7. Overshoot and undershoot specifications are characterized and are not 100% tested.
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05601 Rev. *D
Page 3 of 11
PRELIMINARY
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
GND
10%
ALL INPUT PULSES
90%
90%
10%
CYU01M16SCE
MoBL3™
Rise Time = 1 V/ns
Equivalent to:
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
3.0V (V
CC
)
26000
26000
13000
1.50
Switching Characteristics
Over the Operating Range
[9, 10, 11, 14, 15]
70 ns
Parameter
Read Cycle
t
RC[13]
t
CD
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
Read Cycle Time
Chip Deselect Time CE
1
= HIGH or
CE
2
=LOW, BLE/BHE High Pulse Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[10, 11, 12]
OE HIGH to High Z
[10, 11, 12]
CE LOW to Low Z
[10, 11, 12]
CE HIGH to High Z
[10, 11, 12]
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[10, 11, 12]
BLE/BHE HIGH to High Z
[10, 11, 12]
5
25
10
25
70
5
25
5
70
35
70
15
70
40000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
CC(typ.)
/2, input pulse levels
of 0V to V
CC
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
10. At any given temperature and voltage conditions t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. If invalid address signals shorter than min.tRC are continuously repeated for 40
µs,
the device needs a normal read timing (t
RC
) or needs to enter standby state
at least once in every 40
µs.
14. In order to achieve 70-ns performance, the read access must be Chip Enable (CE
1
or CE
2
) controlled. That is, the addresses must be stable prior to Chip Enable
going active.
Document #: 38-05601 Rev. *D
Page 4 of 11
PRELIMINARY
Switching Characteristics
Over the Operating Range
[9, 10, 11, 14, 15]
(continued)
70 ns
Parameter
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
CD
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Chip Deselect Time CE
1
= HIGH or
CE
2
=LOW, BLE/BHE High Pulse Time
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
[10, 11, 12]
WE HIGH to Low-Z
[10, 11, 12]
10
70
60
60
15
0
0
50
60
25
0
Description
Min.
CYU01M16SCE
MoBL3™
Max.
40000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
ns
Note:
15. The internal Write time of the memory is defined by the overlap of WE, CE
1
= V
IL
or CE
2
= V
IH
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
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