CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Ayama™ 10000
Network Search Engine
Cypress Semiconductor Corporation
Document #: 38-02069 Rev. *F
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised July 13, 2004
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CONFIDENTIAL
PRELIMINARY
TABLE OF CONTENTS
CYNSE10512
CYNSE10256
CYNSE10128
1.0 FEATURES .................................................................................................................................... 10
2.0 OVERVIEW .................................................................................................................................... 11
3.0 DEVICE ARCHITECTURE OVERVIEW ......................................................................................... 13
3.1 Data Array, Mask Array and Table Widths ................................................................................ 13
3.2 Data and Mask Addressing ....................................................................................................... 14
3.3 Successful Search and Multiple Match Arbitration .................................................................... 14
4.0 SIGNALS DESCRIPTION .............................................................................................................. 15
5.0 FUNCTIONAL DESCRIPTION ....................................................................................................... 18
5.1 Modes of Operation .................................................................................................................. 18
5.1.1 Non-Enhanced Mode ...................................................................................................................... 18
5.1.2 Enhanced Mode .............................................................................................................................. 18
5.1.2.1 Mini-Key ........................................................................................................................................................ 19
5.1.2.2 Soft Priority ................................................................................................................................................... 19
5.1.2.3 Parity ............................................................................................................................................................. 20
5.1.2.4 MultiSearch ................................................................................................................................................... 22
5.1.2.5 Enhanced Learn Operation .......................................................................................................................... 23
5.2 I/O Interfaces ............................................................................................................................ 23
5.2.1 ASIC Interface ................................................................................................................................. 24
5.2.2 SRAM Interface ............................................................................................................................... 24
5.2.3 Cascade Interface ........................................................................................................................... 24
5.3 Output Signals Default Driver/Last Device Designation (LRAM and LDEV) ............................. 25
5.4 Registers ................................................................................................................................... 25
5.4.1 Comparand Register (CMPR) ......................................................................................................... 26
5.4.2 Global Mask Register (GMR) .......................................................................................................... 26
5.4.3 Search Successful Register (SSR) ................................................................................................. 27
5.4.4 Command Register (COMMAND) ................................................................................................... 28
5.4.5 Information Register (INFO) ............................................................................................................ 30
5.4.6 Read Burst Address Register (RBURREG) .................................................................................... 30
5.4.7 Write Burst Address Register (WBURREG) .................................................................................... 31
5.4.8 Next-free Address Register (NFA) .................................................................................................. 31
5.4.9 Configuration Register (CONFIG) ................................................................................................... 32
5.4.10 Hardware Register (HARDWARE) ................................................................................................ 33
5.4.11 Parity Control Register (PARITY) .................................................................................................. 34
5.4.12 Control Register (CPR[0:15]) ........................................................................................................ 35
5.4.13 Search Result Register (SRR[15:0]) ............................................................................................. 36
5.4.14 Block Mini-Key Register (BMR) ..................................................................................................... 37
5.4.15 Block Priority Register (BPR) ........................................................................................................ 38
5.4.16 Block Parity Register (BPAR) ........................................................................................................ 39
5.4.17 Block NFA Register (BNFA) .......................................................................................................... 39
5.4.18 Block Priority Register Aliases (BPRA) ......................................................................................... 40
5.5 Multi-Hit Description .................................................................................................................. 41
5.6 Clocks ....................................................................................................................................... 42
5.7 Phase-Locked Loop .................................................................................................................. 43
5.8 Pipeline Latency ........................................................................................................................ 43
5.9 DQ Bus Encoding of Ayama 10000 Address Space ................................................................. 43
5.9.1 Addressing the Data Array, Mask Array and External SRAM ......................................................... 44
5.9.2 Addressing the Internal Registers ................................................................................................... 45
Document #: 38-02069 Rev. *F
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CONFIDENTIAL
PRELIMINARY
TABLE OF CONTENTS
(continued)
CYNSE10512
CYNSE10256
CYNSE10128
5.10 Depth Cascading .................................................................................................................... 45
5.10.1 Depth Cascading up to Eight Devices in One Block ..................................................................... 45
5.10.2 Depth Cascading up to 31 Devices in 4 Blocks ............................................................................ 47
5.10.3 Depth Cascading for a FULL Signal .............................................................................................. 47
5.11 Device Selection in a Cascaded System ................................................................................ 48
5.12 Power-up Sequence ............................................................................................................... 49
6.0 OPERATIONS AND TIMING DIAGRAMS ..................................................................................... 50
6.1 Command Encoding ................................................................................................................. 50
6.2 Command Bus Parameters ....................................................................................................... 50
6.2.1 Non-Enhanced Mode (EMODE = 0) ............................................................................................... 50
6.2.2 Enhanced Mode (EMODE = 1) with MultiSearch Disabled (MSE = 0) ............................................ 51
6.2.3 Enhanced Mode (EMODE = 1) with MultiSearch Enabled (MSE = 1) ............................................ 51
6.3 Read Command ........................................................................................................................ 51
6.3.1 Single Read ..................................................................................................................................... 52
6.3.2 Burst Read ...................................................................................................................................... 52
6.3.3 Read Parity ..................................................................................................................................... 53
6.4 Write Command ........................................................................................................................ 53
6.4.1 Single Write ..................................................................................................................................... 54
6.4.2 Burst Write ...................................................................................................................................... 54
6.4.3 Parallel Write ................................................................................................................................... 55
6.5 Search Command ..................................................................................................................... 56
6.5.1 Mixed-size Single Searches with One Device on Tables Configured with Different Widths ........... 56
6.5.2 Mixed-size Multi Searches with One Device on Tables Configured with Different Widths .............. 58
6.5.3 72-bit Single Search for 1 device or cascade up to eight devices ................................................... 60
6.5.4 72-bit MultiSearch for One Device or Cascade Up to Eight Devices .............................................. 65
6.5.5 144-bit Single Search for Cascade Up to 31 Devices ..................................................................... 72
6.5.6 576-bit Single Search for One Device or Cascade up to Eight Devices ......................................... 85
6.5.7 576-bit MultiSearch for One Device or Cascade up to Eight Devices ............................................. 89
6.5.8 Mixed-size Single Searches with 31 Devices on Tables Configured with Different Widths ............ 95
6.5.9 Mixed-size Multi Searches with 8 Devices on Tables Configured with Different Widths ............... 107
6.6 Learn Command ..................................................................................................................... 113
6.6.1 Non-Enhanced Mode .................................................................................................................... 113
6.6.2 Enhanced Mode ............................................................................................................................ 114
6.6.3 Learn Operation on Depth-Cascaded Table ................................................................................. 117
6.7 SRAM PIO Access .................................................................................................................. 121
6.7.1 SRAM Read with a Table of One Device ...................................................................................... 121
6.7.2 SRAM Read with a Table of up to Eight Devices .......................................................................... 122
6.7.3 SRAM Read with a Table of up to 31 Devices .............................................................................. 125
6.7.4 SRAM Write with a Table of One Device ...................................................................................... 127
6.7.5 SRAM Write with a Table of up to Eight Devices .......................................................................... 129
6.7.6 SRAM Write with Table(s) Consisting of up to 31 Devices ........................................................... 131
6.8 Timing Sequences for Back-to-Back Operations .................................................................... 133
6.9 Full Signal Timing Diagram ..................................................................................................... 134
7.0 JTAG (IEEE 1149.1) ..................................................................................................................... 135
8.0 POWER CONSUMPTION ............................................................................................................ 136
9.0 ELECTRICAL SPECIFICATIONS ................................................................................................ 137
Document #: 38-02069 Rev. *F
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CONFIDENTIAL
PRELIMINARY
TABLE OF CONTENTS
(continued)
CYNSE10512
CYNSE10256
CYNSE10128
10.0 AC TIMING PARAMETERS, WAVEFORMS AND TEST CONDITIONS ................................... 138
10.1 AC Timing Parameters and Waveforms with CLK2X ........................................................... 138
10.2 AC Timing Parameters and Waveforms with CLK1X ........................................................... 140
10.3 AC Test Conditions and Output Loads ................................................................................. 143
10.3.1 LVCMOS 2.5V/1.8V .................................................................................................................... 143
10.3.2 HSTL I/II ...................................................................................................................................... 144
11.0 PIN ASSIGNMENT AND PINOUT DIAGRAM ........................................................................... 145
12.0 PACKAGE DIAGRAMS ............................................................................................................. 151
13.0 ORDERING INFORMATION ...................................................................................................... 151
Document #: 38-02069 Rev. *F
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CONFIDENTIAL
PRELIMINARY
LIST OF FIGURES
CYNSE10512
CYNSE10256
CYNSE10128
Figure 2-1. Ayama™ 10000 Block Diagram .......................................................................................... 11
Figure 2-2. Example of Switch/Router Implementation Using Ayama 10000 ........................................ 12
Figure 3-1. Ayama 10000 Database Table Widths ................................................................................ 13
Figure 3-2. Multi-Width Database Configuration Example..................................................................... 13
Figure 3-3. Addressing the Ayama 10000 Data and Mask Arrays......................................................... 14
Figure 5-1. Blocks and Block Registers Association ............................................................................. 19
Figure 5-2. Mini-Key Register Contents................................................................................................. 19
Figure 5-3. Sub-Blocks and Soft Priority Associations .......................................................................... 20
Figure 5-4. Timing Diagram of a DQ Bus Parity Error (288-bit Search, TLSZ=00)................................ 21
Figure 5-5. Timing Diagram of a Core Parity Error (TLSZ=00).............................................................. 22
Figure 5-6. MultiSearch Operation Overview......................................................................................... 22
Figure 5-7. Ayama 10000 I/O Interfaces................................................................................................ 24
Figure 5-8. Comparand Register Selection During Search and Learn Instructions ............................... 26
Figure 5-9. Addressing the Global Mask Register Array ....................................................................... 27
Figure 5-10. Search Successful Register .............................................................................................. 27
Figure 5-11. Command Register ........................................................................................................... 28
Figure 5-12. Information Register .......................................................................................................... 30
Figure 5-13. Read Burst Register .......................................................................................................... 30
Figure 5-14. Write Burst Address Register ............................................................................................ 31
Figure 5-15. Next-free Address Register ............................................................................................... 31
Figure 5-16. Configuration Register....................................................................................................... 32
Figure 5-17. Hardware Register ............................................................................................................ 33
Figure 5-18. Parity Control Register ...................................................................................................... 34
Figure 5-19. Selection of the CPR through GMR Index......................................................................... 35
Figure 5-20. Control Register ................................................................................................................ 35
Figure 5-21. Search Result Register ..................................................................................................... 36
Figure 5-22. Block Mini-Key Register .................................................................................................... 37
Figure 5-23. Block Priority Register ....................................................................................................... 38
Figure 5-24. Block Parity Register ......................................................................................................... 39
Figure 5-25. Block NFA Register ........................................................................................................... 39
Figure 5-26. Block Priority Register Aliases .......................................................................................... 40
Figure 5-27. Ayama 10000 Clocks (CLK2X and PHS_L) ...................................................................... 42
Figure 5-28. Ayama 10000 Clocks (CLK1X).......................................................................................... 42
Figure 5-29. Ayama 10000 Clocks for All Timing Diagrams .................................................................. 42
Figure 5-30. Data Array, Mask Array and External SRAM Address Space Encoding ........................... 44
Figure 5-31. Internal Register Address Space Encoding....................................................................... 45
Figure 5-32. Depth Cascading in a Single Block ................................................................................... 46
Figure 5-33. Depth Cascading 4 Blocks ................................................................................................ 47
Figure 5-34. FULL Signal Generation in a Cascaded Table.................................................................. 48
Figure 5-35. Proper Power-up Sequence .............................................................................................. 49
Figure 6-1. Single-Location Read Cycle Timing .................................................................................... 52
Figure 6-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ......................................................... 53
Figure 6-3. Single Write Cycle Timing ................................................................................................... 54
Figure 6-4. Burst Write of the Data and Mask Arrays (BLEN = 4) ......................................................... 55
Figure 6-5. Timing Diagram for Mixed Single Search (One Device)...................................................... 57
Figure 6-6. Multiwidth Configurations Using CYNSE10512 as an Example .......................................... 58
Figure 6-7. Timing Diagram for Mixed MultiSearch (One Device) ......................................................... 59
Figure 6-8. Multiwidth Configurations Using CYNSE10512 as an Example .......................................... 60
Figure 6-9. Hardware Diagram for a Table with Eight Devices.............................................................. 61
Document #: 38-02069 Rev. *F
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