Latch-up Current.................................................... > 200 mA
Operating Range
Ambient
Temperature
V
CC
Industrial –40°C to +85°C 2.7V to 3.3V
Electrical Characteristics
Over the Operating Range
CY62136CV30-55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current GND < V
I
< V
CC
Output Leakage
Current
V
CC
Operating Supply
Current
GND < V
O
< V
CC
, Output Disabled
f = f
Max
= 1/t
RC
f = 1 MHz
V
CC
= 3.3V
I
OUT
= 0 mA
CMOS Levels
Test Conditions
I
OH
= –1.0 mA
I
OL
= 2.1 mA
V
CC
= 2.7V
V
CC
= 2.7V
2.2
–0.3
–1
–1
7
1.5
2
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+1
15
3
10
2.2
–0.3
–1
–1
5.5
1.5
2
Typ.
[2]
Max.
CY62136CV30-70
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+1
12
3
10
µA
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
Automatic CE
CE > V
CC
– 0.2V
Power-down Current — V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
CMOS Inputs
f = f
Max
(Address and Data Only),
f = 0 (OE, WE, BHE, and BLE)
Automatic CE
CE > V
CC
– 0.2V
Power-down Current — V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
CMOS Inputs
f = 0, V
CC
= 3.3V
I
SB2
2
10
2
10
µA
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= V
CC(typ.)
Max.
6
8
Unit
pF
pF
Thermal Resistance
[7]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 x 4.5 inch,
2-layer printed circuit board
VFBGA
55
16
Unit
°C/W
°C/W
Notes:
5. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
> 100
µs.
Document #: 38-05199 Rev. *E
Page 3 of 12
CY62136CV30 MoBL
®
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
R2
V
CC
Typ
10%
GND
Rise TIme: 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time: 1 V/ns
Parameters
R1
R2
R
TH
V
TH
3.0V
1105
1550
645
1.75
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[7]
t
R[7]
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V, CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
0
t
RC
Conditions
Min.
1.5
1
Typ.
[2]
Max.
V
cc(max)
6
Unit
V
µA
ns
ns
Chip Deselect to Data
Retention Time
Operation Recovery Time
Data Retention Waveform
DATA RETENTION MODE
V
CC
V
CC(min)
t
CDR
V
DR
> 1.5 V
V
CC(min)
t
R
CE
Document #: 38-05199 Rev. *E
Page 4 of 12
CY62136CV30 MoBL
®
Switching Characteristics
Over the Operating Range
[8]
55 ns
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[9, 10]
WE HIGH to Low-Z
[9]
10
55
45
45
0
0
40
50
25
0
20
10
70
60
60
0
0
45
60
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[9]
OE HIGH to High-Z
[9, 10]
CE LOW to Low-Z
[9]
CE HIGH to High-Z
[9, 10]
CE LOW to Power-up
CE HIGH to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z
[9]
BHE/BLE HIGH to High-Z
[9, 10]
5
20
0
55
25
5
25
10
20
0
70
35
5
20
10
25
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
70 ns
Max.
Unit
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
/I
OH
and 30 pF load capacitance.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
10. It
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
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