S-77100/77101 Series
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© ABLIC Inc., 2015
POWER SEQUENCER
Rev.1.0
_02
The S-77100/77101 Series is a power sequencer.
The S-77100 Series can output enable signals of 4 channels, and controls the external power supply circuit. The S-77100
Series turns on and off the enable signals successively by changing "H" and "L" of the ON pin.
The S-77101 Series can output enable signals of 3 channels, and controls the external power supply circuit. The S-77101
Series turns on the enable
_______
signals successively by changing the ON pin from "L" to "H", and turns off the enable signals
successively by changing OFF pin from "H" to "L".
The delay time for each enable signal can be set by the external capacitor.
Also, the small 8-Pin TSSOP or SNT-8A package makes high-density mounting possible.
Features
Easy support for sequencing of multiple power supplies.
Delay time can be set by the external capacitor.
Sequence operations of 4 channels can be controlled by 1 input signal. (S-77100 Series)
On-sequence operation and off-sequence operation can be controlled by the separate input signal. (S-77101 Series)
Enable output can be increased by cascade connection.
Low current consumption:
3.0
A
typ. (Off period, power-good period, V
DD
= 3.3 V, Ta =
25°C)
Wide range of operation voltage:
2.2 V to 5.5 V
Operation temperature range:
Ta =
40°C
to
85°C
Output form is selectable:
CMOS output, Nch open-drain output
Output logic is selectable:
Active "H", active "L"
Lead-free (Sn 100%), halogen-free:
Applications
Power sequencing for multiple devices
Sequencing for microprocessor and microcontroller
Power sequencing for FPGA
Power sequencing for TV, camera, printer, etc.
Packages
8-Pin TSSOP
SNT-8A
1
POWER SEQUENCER
S-77100/77101 Series
Block Diagrams
1. S-77100 Series
Rev.1.0
_02
ON
Status control circuit
UVLO
*1
ENBL_A
CDLY
Comparator
Charge /
discharge
selection
circuit
ENBL_B
Latch
circuit
ENBL_C
VDD
VSS
ENBL_D
*1.
Selectable as the option
Figure 1
2. S-77101 Series
ON
Status control circuit
OFF
*1
UVLO
ENBL_A
CDLY
Comparator
Charge /
discharge
selection
circuit
Latch
circuit
ENBL_B
VDD
VSS
ENBL_C
*1.
Selectable as the option
Figure 2
2
Rev.1.0
_02
Product Name Structure
POWER SEQUENCER
S-77100/77101 Series
Users can select the presence of the OFF pin, order of enable output, and output form, etc. for the S-77100/77101
Series. Refer to "1.
Product name"
regarding the contents of product name, "2.
Product option list"
regarding the
product type, "3.
Packages"
regarding the package drawings.
_______
1.
Product name
S-7710
x
x
xx
-
xxxx
U
4
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications
*1
T8T1: 8-Pin TSSOP, Tape
I8T1: SNT-8A, Tape
Option code 2
*2
Option code 1
A:
Reverse type
B:
Forward type
Number of channel
_______
0:
4 channels (without OFF pin)
_______
1:
3 channels (with OFF pin)
*1.
*2.
Refer to the tape drawing.
Code added by the optional function that is user-selected.
Refer to "2.
Product option list"
for the kinds of options.
Please contact our sales office for the option code 2.
Refer to "2.
Product option list".
*3
*3.
2.
Product option list
Table 1
Option
Description
The order that the enable output (ENBL_x pin) inverts during off-sequence period can be
selected.
The S-77100 Series
A: The ENBL_D pin, the ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to
"L" in turn.
B: The ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin change to
"L" in turn.
The S-77101 Series
A: The ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to "L" in turn.
B: The ENBL_A pin, the ENBL_B pin and the ENBL_C pin change to "L" in turn.
Option for the delay time (t
DLY
) adjustment.
The number of times of C
DLY
charge and discharge can be selected.
2 times / 4 times / 8 times / 16 times
This datasheet describes the example when "4 times" is selected.
_______
Input level of the ON pin and the OFF pin can be selected.
Schmitt trigger input / Comparator input
Output form of the ENBL_x pin can be selected.
CMOS output / Nch open-drain output
Output logic of the ENBL_x pin can be selected.
Active "H": The type which is "H" during power-good period. /
Active "L": The type which is "L" during power-good period.
This datasheet describes the example when active "H" is selected.
Order of enable output
(Option code 1)
Number of times of
external capacitor (C
DLY
)
charge and discharge
(Option code 2)
Input level
(Option code 2)
Output form
(Option code 2)
Output logic
(Option code 2)
3
POWER SEQUENCER
S-77100/77101 Series
3.
Packages
Table 2
Package Name
8-Pin TSSOP
SNT-8A
Dimension
FT008-A-P-SD
PH008-A-P-SD
Package Drawing Codes
Tape
FT008-E-C-SD
PH008-A-C-SD
Reel
FT008-E-R-S1
PH008-A-R-SD
Rev.1.0
_02
Land
PH008-A-L-SD
Pin Configurations
1. 8-Pin TSSOP
Top view
1
2
3
4
8
7
6
5
Table 3
Pin No.
1
2
3
4
5
Symbol
Description
Enable signal output pin
Enable signal output pin
External capacitor (C
DLY
) connection pin
GND pin
Enable trigger input pin
Enable signal output pin
Disable trigger input pin
Enable signal output pin
Positive power supply pin
ENBL_A
ENBL_B
CDLY
VSS
ON
*1
ENBL_D
_______
6
OFF
*2
7
ENBL_C
8
VDD
*1.
The S-77100 Series only
*2.
The S-77101 Series only
Figure 3
2. SNT-8A
Top view
1
2
3
4
8
7
6
5
Table 4
Symbol
ENBL_A
ENBL_B
CDLY
VSS
ON
*1
ENBL_D
_______
6
OFF
*2
7
ENBL_C
8
VDD
*1.
The S-77100 Series only
*2.
The S-77101 Series only
Pin No.
1
2
3
4
5
Description
Enable signal output pin
Enable signal output pin
External capacitor (C
DLY
) connection pin
GND pin
Enable trigger input pin
Enable signal output pin
Disable trigger input pin
Enable signal output pin
Positive power supply pin
Figure 4
4
Rev.1.0
_02
Pin Functions
1.
ON pin
POWER SEQUENCER
S-77100/77101 Series
This is a trigger input pin to start the sequence operation.
In the S-77100 Series, the on-sequence operation is performed when the rising signal is detected. The
off-sequence operation is performed when the falling signal is detected.
In the S-77101 Series, the on-sequence operation is performed when the rising signal is detected.
Refer to "1.
Sequence operation"
in "
Operation"
for details.
2.
OFF pin (S-77101 Series only)
This is a trigger input pin to start the off-sequence operation. The off-sequence operation is performed when the
falling signal is detected. Refer to "1.
Sequence operation"
in "
Operation"
for details.
_______
3.
ENBL_A, ENBL_B, ENBL_C, ENBL_D pins (ENBL_D pin is S-77100 Series only)
These are pins to output the enable signals to the external power supply circuits.
The ENBL_x pin output form of Nch open-drain output / CMOS output can be selected as the option. Moreover, the
ENBL_x pin output logic of active "H" / active "L" can be selected as the option.
Refer to "1.
Sequence operation"
in "
Operation"
for the sequence operation, "2.
Product option list"
in
"
Product Name Structure"
for the options.
4.
CDLY pin
This is a pin for connecting the external capacitor (C
DLY
) in order to generate the delay time (t
DLY
) of the
on-sequence operation and the off-sequence operation. C
DLY
is charged and discharged by the constant current
circuit.
The charge-discharge operation starts when the ON pin rises, the period from the starting to the ENBL_A pin rising
is t
DLY
which is generated by the S-77100/77101 Series.
Refer to "1.
Sequence Operation"
in "
Operation"
for the operation timing, "
Relation between Delay Time
and External Capacitor"
for the delay time.
5.
VDD pin
Connect this pin with a positive power supply. Refer to "
Electrical Characteristics"
for the values of voltage to be
applied.
6.
VSS pin
Connect this pin to GND.
5
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