The divider ratio for this output is set by FB_SEL(0:2). See
Table 1
on page 1. A bypass delay capacitor at this output will control Input
Reference/ Output Banks phase relationships.
Synchronous Pulse Output.
This output is used for system
synchronization. The rising edge of the output pulse is in sync with
both the rising edges of QA (0:3) and QC(0:3) output clocks
regardless of the divider ratios selected.
PU
PU
PU
PU
PU
Frequency Select Inputs.
These inputs select the divider ratio at
QA(0:3) outputs. See
Table 2.
Frequency Select Inputs.
These inputs select the divider ratio at
QB(0:3) outputs. See
Table 2.
Frequency Select Inputs.
These inputs select the divider ratio at
QC(0:3) outputs. See
Table 2.
Feedback Select Inputs.
These inputs select the divide ratio at
FB_OUT output. See
Table 1
on page 1.
VCO Divider Select Input.
When set LOW, the VCO output is
divided by 2. When set HIGH, the divider is bypassed. See
Table 1
on page 1.
Feedback Clock Input.
Connect to FB_OUT for accessing the PLL.
PLL Enable Input.
When asserted HIGH, PLL is enabled; when
LOW, PLL is bypassed.
Reference Select Input.
When HIGH, the crystal oscillator is
selected; when LOW, TCLK (0,1) is the reference clock.
TCLK Select Input.
When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
Master Reset/Output Enable Input.
When asserted LOW, resets
all of the internal flip-flops and also disables all of the outputs. When
pulled high, releases the internal flip-flops from reset and enables all
of the outputs.
Inverted Clock Input.
When set HIGH, QC(2,3) outputs are
inverted. When set LOW, the inverter is bypassed.
Serial Clock Input.
Clocks data at SDATA into the internal register.
Serial Data Input.
Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
3.3V power supply for output clock buffers.
3.3V power supply for PLL.
Common ground.
25
SYNC
V
DDC
O
42, 43
40, 41
19, 20
5, 26, 27
52
SELA(1,0)
SELB(1,0)
SELC(1,0)
FB_SEL(2:0)
VCO_SEL
I
I
I
I
I
31
6
7
8
2
FB_IN
PLL_EN
REF_SEL
TCLK_SEL
MR#/OE
I
I
I
I
I
PU
PU
PU
PU
PU
14
3
4
INV_CLK
S
CLK
S
DATA
I
I
I
PU
PU
PU
17, 22, 28,
33,37, 45, 49
13
1, 15, 24, 30,
35, 39, 47, 51
V
DDC
V
DD
V
SS
Note:
2. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07290 Rev. *C
Page 2 of 8
CY29972
Description
The CY29972 has an integrated PLL that provides low skew
and low jitter clock outputs for high-performance micropro-
cessors. Three independent banks of four outputs and an
independent PLL feedback output (FB_OUT) provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the V
CO
is configured to
run between 200 MHz and 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input (FB_IN) is connected to the feedback output
(FB_OUT). The internal V
CO
is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select
inputs (refer to Frequency Table). The V
CO
frequency is then
divided to provide the required output frequencies. These
dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select
inputs (see
Table 2
below). For situations were the V
CO
needs
to run at relatively low frequencies and hence might not be
stable, assert VCO_SEL low to divide the VCO frequency by
2. This will maintain the desired output relationships but will
provide an enhanced PLL lock range.
The CY29972 is also capable of providing inverted output
clocks. When INV_CLK is asserted HIGH, QC2 and QC3
output clocks are inverted. These clocks could be used as
feedback outputs to the CY29972 or a second PLL device to
generate early or late clocks for a specific design. This
inversion does not affect the output to output skew.
Glitch-Free Output Frequency Transitions
Customarily, when output buffers have their internal counters
changed “on the fly,” their output clock periods will:
1. contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the
old or new frequencies to which the cycles are being transi-
tioned.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequencies to which the cycles are being transi-
tioned.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
Table 2.
VCO_SEL
0
0
0
0
1
1
1
1
SELA1
0
0
1
1
0
0
1
1
SELA0
0
1
0
1
0
1
0
1
QA
VCO/8
VCO/12
VCO/16
VCO/24
VCO/4
VCO/6
VCO/8
VCO/12
SELB1
0
0
1
1
0
0
1
1
SELB0
0
1
0
1
0
1
0
1
QB
VCO/8
VCO/12
VCO/16
VCO/20
VCO/4
VCO/6
VCO/8
VCO/10
SELC1
0
0
1
1
0
0
1
1
SELC0
0
1
0
1
0
1
0
1
QC
VCO/4
VCO/8
VCO/12
VCO/16
VCO/2
VCO/4
VCO/6
VCO/8
Document #: 38-07290 Rev. *C
Page 3 of 8
CY29972
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other, the SYNC output provides a
signal for system synchronization. The CY29972 monitors the
relationship between the QA and QC output clocks. It provides
a LOW-going pulse, one period in duration, one period prior to
the coincident rising edges of the QA and QC outputs. The
VCO
1:1 Mode
QA
QC
SYNC
2:1 Mode
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
QA
QC
SYNC
4:1 Mode
QC
QA
SYNC
4:3 Mode
QA
QC
SYNC
6:1 Mode
QA
QC
SYNC
duration and placement of the pulse depend on the higher of
the QA and QC output frequencies. The following timing
diagram illustrates various waveforms for the SYNC output.
Note that the SYNC output is defined for all possible combina-
tions of QA and QC outputs, even though under some relation-
ships the lower frequency clock could be used as a synchro-
nizing signal.
Figure 1. Timing Diagram
Document #: 38-07290 Rev. *C
Page 4 of 8
CY29972
Power Management
The individual output enable/freeze control of the CY29972
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
‘0’ state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
data. An output is frozen when a logic ‘0’ is programmed and
enabled when a logic ‘1’ is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial “runt” clocks.
The serial input register is programmed through the SDATA
input by writing a logic ‘0’ start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Figure 2.
Table 3. Suggested Oscillator Crystal Parameters
Parameter
T
C
T
S
T
A
C
L
R
ESR
Characteristic
Frequency Tolerance
Frequency Temperature Stability
Aging
Load Capacitance
Effective Series Resistance (ESR)
Min.
–
–
–
–
–
Typ.
–
–
–
20
40
Max.
±100
±100
5
–
80
Unit
PPM
PPM
PPM/Yr
pF
Ohms
Note 3
(T
A
–10 to +60°C)
[3]
(first 3 years @ 25°C)
[3]
The crystal’s rated load.
[3]
Note 4
Conditions
Absolute Maximum Ratings
[5]
Maximum input voltage relative to V
SS
: .............. V
SS
– 0.3V
Maximum input voltage relative to V
DD
: ............... V
DD
+ 0.3V
Storage temperature: .................................. –65°C to +150°C
Operating temperature:................................. –40°C to +85°C
Maximum ESD protection ................................................ 2kV
Maximum power supply: .................................................5.5V
Maximum input current: .............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD .
Unused inputs must always be tied
to an appropriate logic voltage level (either V
SS
or V
DD
).
Note:
3. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these specifications.
4. Larger values may cause this device to exhibit oscillator start-up problems.
5.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
