CY28551
Universal Clock Generator for Intel, VIA,
and SIS
®
Features
•
•
•
•
•
•
•
•
•
•
•
Compliant to Intel
®
CK505
Selectable CPU clock buffer type for Intel P4 or K8 selection
Selectable CPU frequencies
Universal clock to support Intel, SiS and VIA platform
0.7V Differential CPU clock for Intel CPU
3.3V Differential CPU clock for AMD K8
100 MHz differential SRC clocks
96 MHz differential dot clock
133 MHz Link clock
48 MHz USB clock
33 MHz PCI clocks
•
•
•
•
•
•
•
Dynamic Frequency Control
Dial-A-Frequency
®
WatchDog Timer
Two Independent Overclocking PLLs
Low-voltage frequency select input
I
2
C support with readback capabilities
Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 64-pin QFN package
CPU
x2
SRC
x8
SATA
x1
PCI
x7
REF
x3
LINK
x2
DOT96
x1
24_48M
x1
48M
x1
Block Diagram
VDD_REF
Xin
Xout
Pin Configuration
REF[2:0]
VDD_CPU
CPUT[1:0]
CPUC[1:0]
VDD_PCIEX
PCIET [8:1]
PCIEC[8:1]
VDD_SATA
PCI1/CLKREQ#A
PCI0/CLKREQ#B
**DOC1
PCI4/*SELP4_K8
REF1 /**FSC
PCI5/*SEL0
PCI2/**FSA
PLL Reference
REF2/**MODE
14.318M
Hz
Crystal
RESET_I#/ SRESET#
REF0/ **FSD
PC3/*FSB
VSSREF
VDDPCI
VSSPCI
PLL1
CPU
DOC[2:1]
FS[D:A]
SEL_P4_K8
Divider
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PCI6_F 1
VDD48 2
**SEL24_48 / 24_48M 3
**SEL1/48M 4
VSS48 5
VDDDOT 6
LINK0/DOT96T/SATAT 7
LINK1/DOT96C/SATAC 8
VSSDOT 9
VDDSATA 10
SATAT/PCIEXT0 11
SATAC/PCIEXC0 12
VSSSATA 13
PCIEXT1 14
PCIEXC1 15
VSSPCIE 16
VSSPCIE
VDDPCIE
PCIEXC2
PCIEXC3
PCIEXT2
PCIEXT3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSSPCIE
PCIEXC6
PCIEXC7
PCIEXT5
PCIEXT6
PCIEXT7
VDDREF
SCLK
SDATA
VTTPWRG#/PD
CPUT0
CPUC0
VDDCPU
CPUT1
CPUC1
VSSCPU
**DOC2
VSSA
VDDA
PCIEXT8/CPU_STP#
PCIEXC8/PCI_STP#
VDDPCIE
PCIET0 /SATAT
PCIEC0 /SATAC
PLL2
PCIEX
Divider
M
ultiplexer
Controller
SEL[1:0]
VDD_DO
T
DO
T96T/SATAT/LINK0
DO
T96C/SATAC/LINK1
CY28551
PLL3
SATA
Divider
VDD_PCI
PCI[6:0]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDPCIE
PCIEXC4
PCIEXC5
PCIEXT4
PLL4
Fixed
TPW
R_GD#/PD
SEL24_48
RESET_I#
SDATA
SCLK
Divider
VDD_48
48M
24_48M
I2C
Logic
* Indicates internal pull up
** indicates internal pull down
W
DT
SRESET#
Cypress Semiconductor Corporation
Document #: 001-05675 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 26, 2006
XOUT
XIN
CY28551
Pin Description
Pin No.
1
2
3
Name
PCI6_F
VDD48
Type
O
PWR
Free running 33 MHz clock output.
Intel Type-3A output buffer
3.3V power supply for outputs.
Description
**SEL24_48#/24_4 I/O, PD 3.3V tolerant input for 24 MHz, 48 MHz selection/24_48MHz clock output. Internal
8M
150k pull down
1 = 24 MHz, 0 = 48 MHz
Intel Type-3A output buffer
**SEL1/48MHz
I/O, PD 3.3V tolerant input for output selection/48MHz clock output. Refer to
Table 1
for
selection options
Internal 150k pull down
GND
PWR
Ground for outputs
3.3V Power supply for outputs
4
5
6
7,8
VSS48
VDDDOT
O,
Link output for VIA and SIS, differential 96 MHz clock output and 100 MHz differential
LINK0/DOT96T/SA
TAT
SE/DiF clock. The output is selected by SEL[1:0]
LINK1/DOT96C/SA
TAC
VSSDOT
VDDSATA
GND
PWR
Ground for outputs
3.3V Power supply for outputs
9
10
11,12
13
14,15
16
17,18
19
20,21
22
23,24
25
26,27,28,29
30
31,32
33
34,35
PCIEX0[T/C]/SATA O, DIF Differential SRC clock output/Differential SATA SRC clock output
[T/C]
Intel Type-SR output buffer
VSSSATA
PCIEX[T/C]1
VSSPCIE
PCIEX[T/C]2
VDDPCIE
PCIEX[T/C]3
VSSPCIE
PCIEX[T/C]4
VDDPCIE
PCIEX[T/C][5:6]
VSSPCIE
PCIEX[T/C]7
VDDPCIE
GND
GND
PWR
GND
PWR
GND
PWR
Ground for outputs
Ground for outputs
3.3V power supply for outputs.
Ground for outputs
3.3V power supply for outputs
Ground for outputs
3.3V power supply for outputs
3.3V-tolerant input for stopping PCI and SRC outputs/3.3V-tolerant input for
stopping CPU outputs/100-MHz Differential serial reference clocks.
The two multifunction pins are selected by MODE. Default PCIEX8
Intel Type-SR output buffer
3.3V Power supply for PLL.
Ground for PLL.
Dynamic Over Clocking pin
0 = normal, 1 = Frequency will be changed depend on DOC register. Internal 150k
pull-down.
Ground for outputs.
3.3V Power supply for outputs+
O, DIF 100 MHz Differential serial reference clock. Intel Type-SR output buffer
O, DIF 100 MHz Differential serial reference clock. Intel Type-SR output buffer
O, DIF 100 MHz Differential serial reference clock. Intel Type-SR output buffer
O, DIF 100 MHz Differential serial reference clock. Intel Type-SR output buffer
O, DIF 100 MHz Differential Serial reference clock. Intel Type-SR output buffer
O, DIF 100 MHz Differential Serial reference clock. Intel Type-SR output buffer
PCIEXT8/CPU_ST I/O, DIF
OP#
PCIEXC8/PCI_ST
OP#
VDDA
VSSA
**DOC2
PWR
GND
I, PD
36
37
38
39
40,41
42
43, 44
VSSCPU
CPU[T/C]1
VDDCPU
CPU[T/C]0
GND
PWR
O, DIF Differential CPU clock output. Intel Type-SR output buffer.
O, DIF Differential CPU clock output. Intel Type-SR output buffer.
Page 2 of 30
Document #: 001-05675 Rev. *C
CY28551
Pin Description
(continued)
Pin No.
45
Name
VTT_PWRGD#/PD
Type
I
Description
3.3V LVTTL input. This pin is a level-sensitive strobe used to latch the HW strapping
pin inputs. After asserting VTT_PWRGD# (active LOW), this pin becomes a
real-time input for asserting power-down (active HIGH).
SMBus compatible SDATA
SMBus compatible SCLOCK.
3.3V Power supply for outputs
14.318 MHz Crystal Output
14.318 MHz Crystal Input
Ground for outputs
46
47
48
49
50
51
52
53
SDATA
SCLK
VDDREF
XOUT
XIN
VSSREF
REF2
**FSC/REF1
I/O
I
PWR
O
I
GND
O, SE 14.318 MHz REF clock output.
Intel Type-5 output buffer
I/O,PD, 3.3V tolerant input for CPU frequency selection/14.318 MHz REF clock output
SE
Internal 150k pull down
Intel Type-5 output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
I/O,PD, 3.3V tolerant input for CPU frequency selection/14.318 MHz REF clock output
SE
Internal 150k pull down
Intel Type-5 output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
54
**FSD/REF0
55
56
RESET_I#/SRESE I/O, OD 3.3V tolerant input for reset all of registers to default setting
T#
3.3V LVTTL output for watchdog reset signal
**DOC1
I, PD
Dynamic Over Clocking pin
0 = normal; 1 = Frequency will be changed depend on DOC register. Internal 150k
pull-down
57
PCI0/**CLKREQ#B I/O,SE, 33 MHz clock output/Output enable control for PCIEX4; 5 via I2C register
PD Default is PCI0
0 = Selected PCIEXs are enabled, 1 = Selected PCIEXs are disabled. Internal 150k
pull down
Intel Type-3A output buffer
PCI1/**CLKREQ#A I/O,SE, 33 MHz clock output/Output enable control for PCIEX6, 7via I2C register. Default is
PD PCI1
0 = Selected PCIEXs are enabled, 1 = Selected PCIEXs are disabled. Internal 150k
pull down
Intel Type-3A output buffer
VSSPCI
**FSA/PCI2
GND
Ground for outputs.
I/O, PD 3.3V tolerant input for CPU frequency selection/33 MHz clock output. Internal 150k
pull down
Intel Type-3A output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
I/O, PU 3.3V tolerant input for CPU frequency selection/33 MHz clock output. Internal 150k
pull up
Intel Type-3A output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
PWR
3.3V power supply for outputs.
I/O, PU 3.3V tolerant input for CPU clock output buffer type selection/33 MHz clock output.
Internal 150k pull up
Intel Type-3A output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
0 = K8 CPU buffer type, 1 = P4 CPU buffer type.
I/O, PU 3.3V tolerant input for output selection/33 MHz clock output. Refer to
Table 1
for
selection options.
Internal 150k pull up
Page 3 of 30
58
59
60
61
*FSB/PCI3
62
63
VDDPCI
*SELP4_K8/PCI3
64
*SEL0/PCI5
Document #: 001-05675 Rev. *C
CY28551
Table 1. Frequency Select Table
FSD
FSC
FSB
FSA
CPU0
CPU1
SRC
LINK
66.6667
66.6667
66.6667
66.6667
66.6667
66.6667
66.6667
66.6667
Frequency Table (ROM)
PCI
33.3333
33.3333
33.3333
CPU VCO
800
800
800
CPU PLL
SRC PLL
Gear
CPU CPU PCIE
PCIE PCIE
Gear
Constant M
N
VCO
M
N
Constant
(G)
80
40
60
60
120
30
120
60
80
40
60
60
120
30
120
60
60
60
60
63
63
60
60
60
60
60
60
63
63
60
60
60
200
200
200
175
175
200
200
250
200
200
200
175
175
200
200
250
800
800
800
800
800
800
800
800
800
800
800
800
800
800
800
800
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
FSEL3 FSEL2 FSEL1 FSEL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
266.6666667 266.6666667 100
133.3333333 133.3333333 100
200
200
100
166.6666667 166.6666667 100
333.3333333 333.3333333 100
100
400
200
100
400
250
100
100
100
33.3333 666.6666667
33.3333 666.6666667
33.3333
33.3333
33.3333
800
800
1000
800
800
800
266.6666667 266.6666667 100 133.3333 33.3333
133.3333333 133.3333333 100 133.3333 33.3333
200
200
100 133.3333 33.3333
166.6666667 166.6666667 100 133.3333 33.3333 666.6666667
333.3333333 333.3333333 100 133.3333 33.3333 666.6666667
100
400
200
100
400
250
100 133.3333 33.3333
100 133.3333 33.3333
100 133.3333 33.3333
800
800
1000
Frequency Select Pins (FS[D:A])
To achieve host clock frequency selection, apply the appro-
priate logic levels to FS_A, FS_B, FS_C, and FS_D inputs
prior to VTT_PWRGD# assertion (as seen by the clock synthe-
sizer). When VTT_PWRGD# is sampled LOW by the clock
chip (indicating processor VTT voltage is stable), the clock
chip samples the FS_A, FS_B, FS_C, and FS_D input values.
For all logic levels of FS_A, FS_B, FS_C, FS_D, and FS_E,
VTT_PWRGD# employs a one-shot functionality, in that once
a valid LOW on VTT_PWRGD# has been sampled, all further
VTT_PWRGD#, FS_A, FS_B, FS_C, and FS_D transitions will
be ignored, except in test mode.
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3,
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Document #: 001-05675 Rev. *C
Page 4 of 30
CY28551
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Document #: 001-05675 Rev. *C
Page 5 of 30
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