CY28331
Clock Generator for AMD™ Hammer
Features
• Supports AMD™ Hammer CPU
• Two differential pairs of CPU clocks
• Eight low-skew/low-jitter PCI clocks
• One free-running PCI clock
• Four low-skew/low-jitter PCI/HyperTransport™ clocks
• One 48M output for USB
• One programmable 24M or 48M for FDC
• Three REF 14.318-MHz clocks
•
Dial-a-Frequency
programmability
• Lexmark Spread Spectrum for optimal electromagnetic
interference (EMI) reduction
• SMBus register-programmable options
• 5V-tolerance SCLK and SDATA lines
• 3.3V operation
• Power management control pins
• 48-pin SSOP package
Table 1. Frequency Table (MHz)
[1]
FS
(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
(default)
1000
1001
1010
1011
1100
1101
1110
1111
PCI_HT
SEL
X
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
CPU
HT66
PCI
High-Z
(All outputs except XOUT are three-stated)
133.9
166.9
200.9
100.0
133.3
166.7
200.0
105.0
110.0
210.0
240.0
270.0
233.3
266.7
300.0
67.0/33.5
66.8/33.4
67.0/33.5
66.7/33.3
66.7/33.3
66.7/33.3
66.7/33.3
70.0/35.0
73.3/36.7
70.0/35.0
60.0/30.0
67.5/33.8
58.3/29.2
66.7/33.3
75.0/37.5
33.5
33.4
33.5
33.3
33.3
33.3
33.3
35.0
36.7
35.0
30.0
33.8
29.2
33.3
37.5
Block Diagram
XIN
XOUT
14.31818MHz
XTAL
REF(0:2)
Pin Configuration
/4
PLL1
USB
/2
SEL#
24_48MHz
SRESET#
FS(0:3)
PCISTOP#
SPREAD
PD#
SCLK
SDATA
PLL2
CPUT(0:1)
CPUC(0:1)
Control
Logic
/N
PCI33_F
*FS0/REF0
VDD
XIN
XOUT
VSS
PCI33HT66_0/*PCI33HT66SEL0#
PCI33HT66_1/*PCI33HT66SEL1#
PCI33_HT66_2
VDD
VSS
PCI33_HT66_3
PCI33_7
PCI33_0
PCI33_1
VSS
VDD
PCI33_2
PCI33_3
VDD
VSS
PCI33_4
PCI33_5
PCISel/PCI33_F
*PCI33_6/PCISTOP#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
*FS1/REF1
VSS
VDD
*FS2/REF2
SRESET#/PD#
VDDA
VSSA
CPUT0
CPUC0
VSS
VDD
CPUT1
CPUC1
VDD
VSS
VSSF
VDDF
**USB/FS3
VSS
VDD
24_48MHz/**SEL#
VSS
SDATA
SCLK
CY28331
STOP
PCI33_(0:7)
*100K Internal Pull-up
**100K Internal Pull-down
CNTL
PCI33_HT66_(0:3)
Note:
1. HCLK, 66 MHz, and 33 MHz are in phase and synchronous at power-up.
Cypress Semiconductor Corporation
Document #: 38-07491 Rev. *E
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 14, 2005
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CY28331
Pin Description
Pin
3
4
41, 37
40, 36
XIN
XOUT
CPUT(0:1)
CPUC(0:1)
Name
PWR
V
DD
V
DD
V
DDC
V
DDC
I/O
I
O
O
O
O
I/O
Description
Oscillator Buffer Input.
Connect to a crystal or to an external clock.
Oscillator Buffer Output.
Connect to a crystal. Do not connect when an
external clock is applied at XIN.
CPU clock outputs 0 and 1:
push-pull “true” output of differential pair.
CPU clock outputs 0 and 1:
push-pull “complement” output of differential
pair.
3.3V PCI clock outputs controlled by PCISTOP#.
PCISel is a strap option during power-up to select Pin 24 functionality:
0: Configure Pin 24 as PCI33_6
1: Configure Pin 24 as PCISTOP# (default 100k internal pull-up)
After power-up, this pin reverts to standard PCI33_F output.
3.3V PCI 33-MHz or HyperTransport 66 clock outputs.
This group is
selectable between 33 MHz and 66 MHz, based on the state of
PCI33HT66SEL[0:1]#.
PCI33 or HT66 select.
This input strap selects the output frequency of
PCI33_HT66 outputs to either 33 MHz or 66 MHz. There is an internal
100Kohm pull-up resistor. After power-up, this pin becomes
PCI33_HT66_[0:1] output.
SEL1
SEL0 PIN6
PIN7
PIN8
PIN11
0
0
HT66_0
HT66_1 HT66_2
HT66_3
0
1
HT66_0
HT66_1 HT66_2
PCI33_3
1
0
HT66_0
HT66_1
PCI33_2
PCI33_3
1
1
HT66_0
PCI33_1 PCI33_2
PCI33_3
3.3V USB clock output at 48 MHz.
At power-up this pin is sensed to
determine the CPU output frequency. There is an internal 100K-ohm
pull-down resistor.
3.3V super I/O clock output.
At power-up this pin is sensed to determine
whether the output is 24 MHz or 48 MHz. There is an internal 100K-ohm
pull-down resistor. This pin will be externally strapped high using a
10K-ohm resistor to V
SS
. 0 = 48 MHz, 1 = 24 MHz.
3.3V reference clock output.
At power-up this pin is sensed to determine
the CPU output frequency. There is an internal 100K-ohm pull-up resistor
for FS0, while FS(1:2) includes 100K ohm pull-up resistors.
Watchdog Time-out Reset Output.
Power-down input (100K internal
pull-up).
When configured through pin 23 as PCI_STOP#, this pin controls the
PCI33(0:5,7) and PCI33_HT66(1:3) outputs.
Active LOW control input to
halt all 33-MHz PCI clocks except PCI33_F. Only the PCI33_HT66 outputs
that are running at 33 MHz will be stopped. The outputs will be glitch-free
when turning off and turning on (100K internal pull-up). When configured
through pin 23 as PCI33_6, PCI_STOP# is unavailable.
3.3V PCI clock outputs controlled by PCISTOP#.
Data pin for SMBus (rev2.0).
There is an internal 100K-ohm pull-up
resistor.
Clock pin for SMBus (rev2.0).
There is an internal 100K-ohm pull-up
resistor.
13, 14, 17, PCI33(0:5)
18, 21, 22
23
PCISel /
PCI33_F
8, 11
PCI33_HT66(2:3)
V
DDD
V
DDD
O
6, 7
PCI33_HT66_[0:1]/
PCI33_HT66SEL[0:1]#
I/O
31
USB/FS3
I/O
28
24_48MHz/SEL#
I/O
1, 48, 45
REF(0:2)/FS(0:2)
I/O
44
24
SRESET#/PD#
PCI33_6/
PCISTOP#
I/O
I/O
12
26
25
PCI33_7
SDATA
SCLK
O
I/O
I
2, 9, 16,
V
DD
19, 29, 35,
38, 46
5, 10, 15, V
SS
20, 27, 30,
34, 39, 47
43
V
DDA
PWR
Power connection to 3.3V for the core.
GND
Power connection to GROUND for the CORE section of the chip.
PWR
Power connection to 3.3V for the ANALOG section of the chip.
Page 2 of 17
Document #: 38-07491 Rev. *E
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CY28331
Pin Description
(continued)
Pin
42
32
33
V
SSA
V
DDF
V
SSF
Name
PWR
I/O
Description
GND
Power connection to GROUND for the analog section of the chip.
PWR
Power connection to 3.3V for the 48-MHz PLL section of the chip.
GND
Power connection to GROUND for the 48-MHz PLL section of the chip.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface (SDI), various device functions, such as
individual clock output buffers, can be individually enabled or
disabled. The registers associated with the SDI initialize to
their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Description
Table 2. Command Code Definition
Bit
7
(6:0)
0 = Block read or block write operation, 1 = Byte read or byte write operation.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits
should be '0000000.'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Data Byte (N–1) – 8 bits
Acknowledge from slave
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
Document #: 38-07491 Rev. *E
Page 3 of 17
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CY28331
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to be
accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Serial Control Registers
Byte 0: Frequency and Spread Spectrum Control Register
Bit
7
@Pup
Inactive = 0
Pin#
Name
Description
Write Disable (write once). A 1 written to this bit after a 1 has been written to Byte0
bit0 will permanently disable modification of all configuration registers until the part
has been powered off. Once the clock generator has been Write Disabled, the
SMBus controller should still accept and acknowledge subsequent write cycles but
it should not modify any of the registers.
For Test, always program to ‘0’
12
31
45
48
1
PCI33_7
FS3
FS2
FS1
FS0
Enable (1 = Enabled, 0 = Disabled)
corresponds to Frequency Selection. See
Table 1.
corresponds to Frequency Selection. See
Table 1.
corresponds to Frequency Selection. See
Table 1.
corresponds to Frequency Selection. See
Table 1.
Write Enable. A 1 written to this bit after power-up will enable modification of all
configuration registers and subsequent 0's written to this bit will disable modification
of all configuration except this single bit. Note that block write transactions to the
interface will complete, however unless the interface has been previously unlocked,
the writes will have no effect. The effect of writing this bit doe not take effect until
the subsequent block write command.
Pin#
23
24
22
21
18
17
14
13
Name
PCI33_F
PCI33_6
PCI33_5
PCI33_4
PCI33_3
PCI33_2
PCI33_1
PCI33_0
Description
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Page 4 of 17
6
5
4
3
2
1
0
0
1
FS3 pin
FS2 pin
FS1 pin
FS0 pin
Inactive = 0
Byte 1: PCI Clock Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Document #: 38-07491 Rev. *E
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CY28331
Byte 2: USB, 24–48MHz, REF(0:2) Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
active = 1
active = 1
active = 1
active = 1
active = 1
active = 1
active = 1
0
Pin #
37, 36
41, 40
45
48
1
28
31
Name
Description
CPUT/C(1) CPUT/C(1) shutdown. This bit can be optionally used to disable the CPUT/C(1)
clock pair. During shutdown, CPUT = low and CPUC = high
CPUT/C(0) CPUT/C(0) shutdown. This bit can be optionally used to disable the CPUT/C(0)
clock pair. During shutdown, CPUT = low and CPUC = high
REF2
REF1
REF0
USB
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
For Test, always program to ‘0’
24_48MHz Enable (1 = Enabled, 0 = Disabled)
Byte 3: PCI Clock Free Running Select Control Register
Bit
7
@Pup
Inactive = 0
Pin #
Name
PCI_DRV
0 = Low Strength
1 = High Strength
PCI33_HT66 Drive Strength
0 = Low Strength
1 = High Strength
22
21
18
11
8
7
PCI5
PCI4
PCI3
Free running enable (10 = Free running, 0 = Disabled)
Free running enable (1 = Free running, 0 = Disabled)
Free running enable (1 = Free running, 0 = Disabled)
Description
6
Inactive = 0
5
4
3
2
1
0
Inactive = 0
Inactive = 0
Inactive = 0
1
1
1
PCI33_HT66_3 Enable (1 = Enabled, 0 = Disabled)
PCI33_HT66_2 Enable (1 = Enabled, 0 = Disabled)
PCI33_HT66_1 Enable (1 = Enabled, 0 = Disabled)
Byte 4: Pin Latched/Real-time State
Bit
7
6
5
4
3
2
1
0
@Pup
1
HW
0
1
FS3 pin
FS2 pin
FS1 pin
FS0 pin
31
45
48
1
Pin#
6
Name
PCI33_HT66_0
Reserved
SSEN
FS3
FS2
FS1
FS0
24_48MHz/SEL# Pin power-up latched state
For Test, always program to ‘0’
Spread Spectrum enable (0 = disable, 1 = enable).
This bit provides a SW programmable control for spread spectrum clocking.
Power-up latched state
Power-up latched state
Power-up latched state
Power-up latched state
Description
Enable (1 = Enabled, 0 = Disabled)
Byte 5: SSCG, Dial-a-Skew™, and Dial-a-Ratio™ Register
Bit
7
6
@Pup
0
1
Spread Spectrum Selection:
bit7
bit6
bit5
% Spread
0
0
0
–1.5
0
0
1
–1.0
0
1
0
–0.7
0
1
1
–0.5 (default)
1
0
0
±0.75
1
0
1
±0.50
1
1
0
±0.35
1
1
1
±0.25
Description
5
1
Document #: 38-07491 Rev. *E
Page 5 of 17
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