Programmable spread spectrum with nominal 31.5 kHz
modulation frequency
Center spread: ±0.25% to ±2.5%
Down spread: –0.5% to –5.0%
Input frequency range
❐
External crystal: 8–30 MHz fundamental crystals
❐
External reference: 8–166 MHz clock
Integrated phase-locked loop (PLL)
Programmable crystal load capacitor tuning array
Low cycle-to-cycle jitter
3.3V operation with 2.5V output clock drive option
Spread spectrum On and Off function
Power down or Output Enable function
Output frequency select option
Field-programmable
Package: 16 pin TSSOP
Suitable for most PC peripherals, networking, and consumer
applications.
Provides wide range of spread percentages for maximum EMI
reduction to meet regulatory agency Electro Magnetic
Compliance (EMC) requirements. Reduces development and
manufacturing costs and time to market.
Eliminates the need for expensive and difficult to use higher
order crystals.
Internal PLL generates up to 200 MHz outputs; also generates
custom frequencies from an external crystal or a driven source.
Enables fine tuning of output clock frequency by adjusting
C
Load
of the crystal. Eliminates the need for external C
Load
capacitors.
Application compatibility in standard and low power systems.
Provides ability to enable or disable spread spectrum with an
external pin.
Enables low power state or output clocks to High-Z state.
Enables quick generation of sample prototype quantities.
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■
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■
■
■
■
■
■
■
■
■
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Logic Block Diagram
7
Divider
Bank 1
Output
Select
Matrix
VCO
SSCLK1
8
SSCLK2
9
SSCLK3
XIN/CLKIN 1
XOUT
16
C
XOUT
OSC.
Q
Φ
12
SSCLK4
C
XIN
P
PLL
Divider
Bank 2
14
SSCLK5/REFOUT/CP2
15
SSCLK6/REFOUT/CP3
2
VDD
3
AVDD
5
AVSS
13
VSS
11
VDDL
6
VSSL
4
CP0
10
CP1
Cypress Semiconductor Corporation
Document #: 38-07633 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 11, 2007
[+] Feedb
CY25200
Pin Configuration
Figure 1. Pin Diagram
General Description
The CY25200 is a Spread Spectrum Clock Generator (SSCG) IC
used to reduce Electro Magnetic Interference (EMI) found in
today’s high speed digital electronic systems.
The device uses a Cypress proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the funda-
mental and harmonic frequencies are greatly reduced. This
reduction in radiated energy significantly reduces the cost of
complying with regulatory agency requirements (EMC) and
improves time to market, without degrading system perfor-
mance.
The CY25200 uses a factory and field-programmable configu-
ration memory array to synthesize output frequency, spread %,
crystal load capacitor, clock control pins, PD#, and OE options.
Table 1. Pin Summary
Name
XIN
XOUT
VDD
AVDD
VSS
AVSS
VDDL
VSSL
SSCLK1
SSCLK2
SSCLK3
SSCLK4
SSCLK5/REFOUT/CP2
SSCLK6/REFOUT/CP3
CP0
[1]
CP1
[1]
Pin Number
1
16
2
3
13
5
11
6
7
8
9
12
14
15
4
10
The spread % is factory and field-programmed to either center
spread or down spread with various spread percentages. The
range for center spread is from ±0.25% to ±2.50%. The range for
down spread is from –0.5% to –5.0%. Contact the factory for
smaller or larger spread % amounts, if required.
The input to the CY25200 is either a crystal or a clock signal. The
input frequency range for crystals is 8–30 MHz and for clock
signals is 8–166 MHz.
The CY25200 has six clock outputs, SSCLK1 to SSCLK6. The
frequency modulated SSCLK outputs are programmed from
3–200 MHz.
The CY25200 products are available in a 16-pin TSSOP
package with a commercial operating temperature range of 0 to
70°C.
Description
Crystal Input or Reference Clock Input
Crystal Output.
Leave this pin floating if external clock is used
3.3V power supply for digital logic and SSCLK5 and 6 clock drives
3.3V analog–PLL power supply
Ground
Analog ground
2.5V or 3.3V power supply for SSCLK1/2/3/4 clock drives
VDDL power supply ground
Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V)
Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V)
Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V)
Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V)
Programmable spread spectrum clock or buffered reference output at VDD level
(3.3V) or control pin, CP2
Programmable spread spectrum clock or buffered reference output at VDD level
(3.3V) or control pin, CP3
Control pin 0
Control pin 1
Note
1. Pins are programmed to be any of the following control signals: OE: Output Enable, OE = 1, all the SSCLK outputs are enabled; PD#: Power down, PD# = 0, all the
SSCLK outputs are three-stated and the part enters a low power state; SSON: Spread Spectrum Control (SSON = 0, No Spread and SSON = 1, Spread Signal),
CLKSEL: SSCLK Output Frequency Select. Please see
Control Pins (CP0, CP1, CP2 and CP3)
for control pins programming options.
Document #: 38-07633 Rev. *D
Page 2 of 12
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CY25200
Table 2. Fixed Function Pins
Pin Function
Pin Name
Pin#
Units
Program Value
CLKSEL = 0
Program Value
CLKSEL = 1
Output Clock Functions and Frequency
SSCLK1
7
MHz
ENTER
DATA
ENTER
DATA
SSCLK2
8
MHz
ENTER
DATA
ENTER
DATA
SSCLK3
9
MHz
ENTER
DATA
ENTER
DATA
SSCLK4
12
MHz
ENTER
DATA
ENTER
DATA
ENTER
DATA
ENTER
DATA
ENTER
DATA
31.5
Input
Frequency
XIN and
XOUT
1 and 16
MHz
C
XIN
and
C
XOUT
XIN and
XOUT
1 and 16
pF
Spread
Percent
SSCLK[1:6]
Frequency
Modulation
SSCLK[1:6]
7,8,9,12,14,15 7,8,9,12,14,15
%
kHz
Table 3. Multi-Function Pins
Pin
Function
Pin Name
Pin#
Units
Program Value
CLKSEL = 0
Program Value
CLKSEL = 1
Output Clock/REFOUT/OE/SSON/CLKSEL
SSCLK5/REFOUT/CP2
14
MHz
ENTER DATA
ENTER DATA
SSCLK6/REFOUT/CP3
15
MHz
ENTER DATA
ENTER DATA
ENTER DATA
ENTER DATA
OE/PD#/SSON/CLKSEL
CP0
4
N/A
CP1
10
N/A
Programming Description
Field-Programmable CY25200
The CY25200 is programmed at the package level, that is, in a
programmer socket. The CY25200 is Flash technology based,
so the parts are reprogrammed up to 100 times. This allows for
fast and easy design changes and product updates, and elimi-
nates any issues with old and out of date inventory.
Samples and small prototype quantities are programmed on the
CY3672 programmer with the CY3695 socket adapter.
and make sure to check the “non-standard devices” box. For
more information on the registration process refer to the CY3672
data sheet.
For information regarding Spread Spectrum software
programming solutions, please contact your local Cypress Sales
or Field Application Engineer (FAE), representative for details.
Factory-Programmable CY25200
Factory programming is available for volume manufacturing by
Cypress. All requests must be submitted to the local Cypress
Field Application Engineer (FAE) or sales representative. The
sample request form provided by the representative must be
completed. When the request is processed, you receive a new
part number, samples, and data sheet with the programmed
values. This part number is used for additional sample requests
and production orders.
Additional information on the CY25200 are available on the
Cypress website at
www.cypress.com.
CyberClocks™ Online Software
CyberClocks™ Online Software is a web based software appli-
cation that allows the user to custom configure the CY25200. All
the parameters in given as “Enter Data” are programmed into the
CY25200. CyberClocks Online outputs an industry standard
JEDEC file used for programming the CY25200. CyberClocks
Online is available at
www.cyberclocksonline.com
website
through user registration. To register, fill out the registration form
Document #: 38-07633 Rev. *D
Page 3 of 12
[+] Feedb
CY25200
Product Functions
Control Pins (CP0, CP1, CP2 and CP3)
There are four control signals available through programming of
pins 4, 10, 14, and 15.
CP0 (pin 4) and CP1 (pin10) are specifically designed to function
as control pins. However pins 14 (SSCLK5/REFOUT/CP2) and
15 (SSCLK6/REFOUT/CP3) are multi-functional and are
programmed to be a control signal or an output clock (SSCLK or
REFOUT). All of the control pins, CP0, CP1, CP2, and CP3 are
programmable and are programmed to have only one of the
following functions:
■
■
■
■
shows an example of how this is implemented. The VCO
frequency range is 100–400MHz. The CY25200 has two
separate dividers, Divider 1 and Divider 2. These two are loaded
to have any number between 2 and 130 providing two different
but related frequencies as explained above.
In the above example SSCLK5 (pin 14) and SSCLK6 (pin 15) are
used as output clocks. However, they can also be used as control
signals. See
Figure 3
for the pinout.
Input Frequency (XIN, pin 1 and XOUT, pin 16)
The input to the CY25200 is a crystal or a clock. The input fre-
quency range for crystals is 8 to 30 MHz, and for clock signal is
8 to 166 MHz.
Output Enable (OE)—if OE = 1, all the SSCLK or REFOUT
outputs are enabled.
SSON, Spread spectrum control—1 = spread on and
0 = spread off.
CLKSEL—SSCLK output frequency select
PD#, Active Low—if PD# = 0, all the outputs are three-stated
and the part enters a low power state.
C
XIN
and C
XOUT
(pin 1 and pin 16)
The load capacitors at pin 1 (C
XIN
) and pin 16 (C
XOUT
) are
programmed from 12 pF to 60 pF with 0.5 pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
The required values of
C
XIN
and
C
XOUT
for matching crystal load
(CL) is calculated using the following formula:
C
XIN
= C
XOUT
= 2C
L
– C
P
Where C
L
is the crystal load capacitor as specified by the crystal
manufacturer and C
P
is the parasitic PCB capacitance.
For example, if a fundamental 16 MHz crystal with C
L
of 16 pF is
used and C
P
is 2 pF, C
XIN
and C
XOUT
is calculated as:
C
XIN
= C
XOUT
= (2 x 16) – 2 = 30 pF.
If using a driven reference clock, set C
XIN
and C
XOUT
to the min-
imum value 12 pF.
The last control signal is the power down (PD#) that is imple-
mented only through programming CP0 or CP1 (CP2 and CP3
cannot be programmed as PD#). Here is an example with three
control pins:
■
■
■
■
■
■
CLKIN = 33 MHz
SSCLK1/2/3/4 = 100 MHz with ±1% spread
SSCLK 5 = REFOUT(33 MHz)
CP0 (Pin 4) = PD#
CP1 (Pin 10) = OE
CP3 (pin 15) = SSON
Figure 2. Pin Diagram
33.0MHz
VDD
AVDD
PD#
AVSS
VSSL
100MHz
100MHz
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
SSON
REFOUT(33.0MHz)
Output Frequency (SSCLK1 through SSCLK6
Outputs)
All of the SSCLK outputs are produced by synthesizing the input
reference frequency using a PLL and modulating the VCO
frequency. SSCLK[1:4] is programmed to be only output clocks
(SSCLK). SSCLK5 and SSCLK6 are also programmed to
function the same as SSCLK[1:4] or a buffered copy of the input
reference (REFOUT) or they are programmed to be a control pin
as discussed in the control pins section. To use the 2.5V output
drive option on SSCLK[1:4], VDDL must be connected to a 2.5V
power supply (SSCLK[1:4] outputs are powered by VDDL).
When using the 2.5V output drive option, the maximum output
frequency on SSCLK[1:4] is 166 MHz.
The pinout for the above example is shown in
Figure 2.
VSS
100MHz
VDDL
OE
100MHz
Spread Percentage (SSCLK1 through SSCLK6
Outputs)
The SSCLK frequency is programmed at any percentage value
from ±0.25% to ±2.5% for center spread and from –0.5% to
–5.0% down spread.
The CLKSEL control pin enables the user to change the output
frequency from one frequency to another (for example,
frequency A to frequency B). These must be related frequencies
that are derived off of a common VCO frequency. For instance,
33.333 MHz and 66.666 MHz are both derived from a VCO of
400 MHz and dividing it down by 12 and 6 respectively.
Table 4
Frequency Modulation
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if a
higher modulation frequency is required.
Document #: 38-07633 Rev. *D
Page 4 of 12
[+] Feedb
CY25200
Table 4. Using Clock Select, CLKSEL Control Pin
Input Frequency
(MHz)
14.318
CLKSEL
(Pin 4)
CLKSEL = 0
CLKSEL = 1
SSCLK1
(Pin 7)
33.33
66.66
SSCLK2
(Pin 8)
33.33
66.66
SSCLK3
(Pin 9)
33.33
66.66
SSCLK4
(Pin 12)
33.33
66.66
REFOUT
(Pin 14)
14.318
14.318
REFOUT
(Pin 15)
14.318
14.318
Figure 3. Using Clock Select, CLKSEL Control Pin Configuration Pinout
板子msp-exp430f5529lp,用的是energia，移植arduino的程序到430上来，interrupt怎么改？
Interrupt.ino: In function 'void interruptSetup()':
Interrupt.ino:17:3: error: 'TCCR2A' was not ......
stm32/stm8
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