PRELIMINARY
Am79C961
PCnet
TM
-ISA
+
Jumperless Single-Chip Ethernet Controller
for ISA
DISTINCTIVE CHARACTERISTICS
s
Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
s
Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
s
Direct interface to the ISA or EISA bus
s
Software compatible with AMD’s Am7990
LANCE register and descriptor architecture
s
Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
s
Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
— Automatic retransmission with no FIFO
reload
— Automatic receive stripping and transmit
padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of received collision
frames
s
Dynamic transmit FCS generation program-
mable on a frame-by-frame basis
s
Single +5 V power supply
s
Internal/external loopback capabilities
s
Supports 8K, 16K, 32K, and 64K Boot PROMs
or Flash for diskless node applications
s
Supports Microsoft’s Plug and Play System
configuration for jumperless designs
s
Supports staggered AT bus drive for reduced
noise and ground bounce
s
Supports 8 interrupts on chip
Advanced
Micro
Devices
s
Look Ahead Packet Processing (LAPP) allows
protocol analysis to begin before end of
receive frame
s
Supports 4 DMA channels on chip
s
Supports 16 I/O locations
s
Supports 16 boot PROM locations
s
Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with 2 modes
of port selection:
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
s
Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
s
Supports bus-master and shared-memory
architectures to fit in any PC application
s
Supports edge and level-sensitive interrupts
s
DMA Buffer Management Unit for reduced CPU
intervention which allows higher throughput by
by-passing the platform DMA
s
JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
s
Integrated Manchester Encoder/Decoder
s
Supports the following types of network
interfaces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
s
Supports LANCE General Purpose Serial
Interface (GPSI)
s
132-pin PQFP package
GENERAL DESCRIPTION
The PCnet-ISA
+
controller, a single-chip Ethernet con-
troller, is a highly integrated system solution for the
PC-AT Industry Standard Architecture (ISA ) architec-
ture. It is designed to provide flexibility and compatibility
with any existing PC application. This highly integrated
132-pin VLSI device is specifically designed to reduce
parts count and cost, and addresses applications where
higher system throughput is desired. The PCnet-ISA
+
Publication#
18183
Rev.
B
Issue Date:
April 1994
Amendment
/0
controller is fabricated with AMD’s advanced low-power
CMOS process to provide low standby current for power
sensitive applications.
The PCnet-ISA
+
controller is a DMA-based device with a
dual architecture that can be configured in two different
operating modes to suit a particular PC application. In
the Bus Master Mode all transfers are performed using
1-475
This document contains information on a product under development at Advanced Micro Devices, Inc.
The information is intended to help you to evaluate this product. AMD reserves the right to change or
discontinue work on this proposed product without notice.
AMD
PRELIMINARY
External remote boot and Ethernet physical address
PROMs and Electrically Erasable Proms are also
supported.
This advanced Ethernet controller has the built-in capa-
bility of automatically selecting either the AUI port or the
Twisted Pair transceiver. Only one interface is active at
any one time. The individual 136-byte transmit and
128-byte receive FIFOs optimize system overhead, pro-
viding sufficient latency during packet transmission and
reception, and minimizing intervention during normal
network error recovery. The integrated Manchester en-
coder/decoder eliminates the need for an external Serial
Interface Adapter (SIA) in the node system. If support
for an external encoding/decoding scheme is desired,
the embedded General Purpose Serial Interface (GPSI)
allows direct access to/from the MAC. In addition, the
device provides programmable on-chip LED drivers for
transmit, receive, collision, receive polarity, link integrity
and activity, or jabber status. The PCnet-ISA
+
controller
also provides an External Address Detection Interface™
(EADI™) to allow external hardware address filtering in
internetworking applications.
the integrated DMA controller. This configuration en-
hances system performance by allowing the
PCnet-ISA
+
controller to bypass the platform DMA con-
troller and directly address the full 24-bit memory space.
The implementation of Bus Master Mode allows mini-
mum parts count for the majority of PC applications. The
PCnet-ISA
+
controller can be configured to perform
Shared Memory operations for compatibility with low-
end machines, such as PC/XTs that do not support Bus
Master and high-end machines that require local packet
buffering for increased system latency.
The PCnet-ISA
+
controller is designed to directly inter-
face with the ISA or EISA system bus. It contains an ISA
Plug and Play bus interface unit, DMA Buffer Manage-
ment Unit, 802.3 Media Access Control function,
individual 136-byte transmit and 128-byte receive
FIFOs, IEEE 802.3 defined Attachment Unit Interface
(AUI), and a Twisted Pair Transceiver Media Attach-
ment Unit. The PCnet-ISA
+
controller is also register
compatible with the LANCE (Am7990) Ethernet control-
ler and PCnet-ISA. The DMA Buffer Management Unit
supports the LANCE descriptor software model.
RELATED PRODUCTS
Part No.
Am79C98
Am79C100
Am7996
Am79C981
Am79C987
Am79C940
Am79C90
Am79C960
Am79C965
Am79C970
Description
Twisted Pair Ethernet Transceiver (TPEX)
Twisted Pair Ethernet Transceiver Plus (TPEX
+
)
IEEE 802.3/Ethernet/Cheapernet Transceiver
Integrated Multiport Repeater Plus™ (IMR+™)
Hardware Implemented Management Information Base™ (HIMIB™)
Media Access Controller for Ethernet (MACE™)
CMOS Local Area Network Controller for Ethernet (C-LANCE)
PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386, 486, VL local buses)
PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
1-476
Am79C961
PRELIMINARY
AMD
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM79C961
K
C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and Formed (PQB132)
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0
°
to +70
°
C)
PACKAGE TYPE
(per Prod. Nomenclature/16-038)
K = Molded Carrier Ring Plastic Quad Flat Pack
(PQB132)
SPEED
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79C961
Valid Combinations
AM79C961
KC, KC\W
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult the local AMD sales office to confirm
availability of specific valid combinations and to
check on newly released combinations.
Am79C961
1-477
AMD
TABLE OF CONTENTS
PRELIMINARY
DISTINCTIVE CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-475
GENERAL DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-475
RELATED PRODUCTS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-476
ORDERING INFORMATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-477
BLOCK DIAGRAM: BUS MASTER MODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-484
CONNECTION DIAGRAM: BUS MASTER
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-484
PIN DESIGNATIONS: BUS MASTER
LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-486
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-487
LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-488
PIN DESCRIPTION: BUS MASTER MODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-490
ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-490
BOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-491
BLOCK DIAGRAM: SHARED MEMORY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-493
CONNECTION DIAGRAM: SHARED MEMORY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-494
PIN DESIGNATIONS: SHARED MEMORY
LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-495
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-496
LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-497
PIN DESCRIPTION: SHARED MEMORY MODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-499
ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-499
BOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-500
PIN DESCRIPTION: NETWORK INTERFACES (mode independent)
. . . . . . . . . . . . . . . . 1-502
AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-502
TWISTED PAIR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-502
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-502
PIN DESCRIPTION: POWER SUPPLIES (mode independent)
. . . . . . . . . . . . . . . . . . . . . 1-502
FUNCTIONAL DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-503
BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-503
SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-505
NETWORK INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-505
PLUG AND PLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-507
DETAILED FUNCTIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-514
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-514
SERIAL EEPROM BYTE MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-515
PLUG AND PLAY REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-517
PLUG AND PLAY REGISTER LOCATIONS DETAILED DESCRIPTION . . . . . . . . . . . 1-518
SHARED MEMORY CONFIGURATION BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-520
USE WITHOUT EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
EXTERNAL SCAN CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
FLASH PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
OPTIONAL IEEE ADDRESS PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
EISA CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
1-478
Am79C961
PRELIMINARY
AMD
BUS INTERFACE UNIT (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
1. Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
2. Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
3. Burst-Cycle DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
BUFFER MANAGEMENT UNIT (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Descriptor Ring Access Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-523
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-523
Transmit Descriptor Table Entry (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-525
Receive Descriptor Table Entry (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-526
MEDIA ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-527
Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . 1-527
Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-528
MANCHESTER ENCODER/DECODER (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
External Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
External Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
Transmitter Timing and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-531
Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-531
Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-531
PLL Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-531
Carrier Tracking and End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Data Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Differential Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Jitter Tolerance Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
TWISTED PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-533
Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-533
Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-533
Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-533
Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . 1-534
Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
EADI™ (External Address Detection Interface™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
GENERAL PURPOSE SERIAL INTERFACE (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-536
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
Am79C961
1-479
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