Product Specification
PE4306
Product Description
The PE4306 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering a 31 dB attenuation range in 1dB steps, and is
pin compatible with the PE430x series. This 50-ohm RF DSA
provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4306 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4306
is manufactured on Peregrine’s UltraCMOS
®
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
RF Input
50Ω RF Digital Attenuator
5-bit, 31 dB, 1 – 4000 MHz
Features
Attenuation: 1 dB steps to 31 dB
Flexible parallel and serial programming
interfaces
Latched or direct mode
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
50Ω impedance
Pin compatible with PE430x series
Packaged in a 20 Lead 4x4 mm QFN
Serial Control
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0V
O
Parameter
Test Conditions
E
W
Frequency
Power-Up Control
BS
C
3
Parallel Control
5
Control Logic Interface
2
O
IT
RF Output
DOC-02145
Switched Attenuator Array
LE
H
PE
T
4x4 mm 20-lead QFN
Minimum
1
-
-
30
-
15
-
1.5
-
34
52
20
-
Typical
1–2200 MHz
1
≤
1000 MHz
1000 < 2200 MHz
1–2200 MHz
1–2200 MHz
1–2200 MHz
Figure 2. Package Type
43
12
Maximum
4000
2.25
±(0.3 + 3% of atten setting)
±(0.3 + 5% of atten setting)
-
-
-
1
E
Units
MHz
dB
dB
dB
dBm
dBm
dB
s
Operation Frequency
Insertion Loss
2
1 dB Compression
3
Input IP3
1, 2
Return Loss
Switching Speed
Document No. DOC-30007-2
│
www.psemi.com
R
Notes: 1. Device linearity will begin to degrade below 1 MHz
2. See max input rating in
Table 3
&
Figures 3-13
for data across frequency
3. Note absolute maximum in
Table 3
EP
LA
Attenuation Accuracy
Any bit or bit
combination
Two-tone inputs
+18 dBm
50% control to 0.5 dB
of final value
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE4306
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0V unless otherwise noted
Figure 3. Insertion Loss
Figure 4. Attenuation at Major steps
0
35
31 dB
30
-1
25
Normalized Error (dB)
Insertion Loss (dB)
-2
20
-3
insertion loss @ 25 C
insertion loss @ -40 C
insertion loss @ 85 C
15
-4
-5
0
500
1000
1500
2000
2500
LE
H
PE
T
10
5
4 dB
2 dB
1 dB
500
0
3000
3500
4000
0
43
12
1000
1500
2000
2500
3000
Frequency (MHz)
E
16 dB
8 dB
3500
4000
Frequency (MHz)
Figure 5. Input Return Loss at Major
Attenuation Steps
0
O
IT
W
3500
4000
Figure 6. Output Return Loss at Major
Attenuation Steps
0
-10
BS
C
16 dB
-10
O
-30
E
S22 (dB)
-20
s11 (dB)
-20
-30
-40
31 dB
31 dB
-40
16 dB
EP
LA
-50
0
500
1000
1500
2000
2500
-50
3000
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Frequency (MHz)
R
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
Document No. DOC-30007-2
│
UltraCMOS
®
RFIC Solutions
PE4306
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0V unless otherwise noted
Figure 7. Attenuation Error vs. Frequency
Figure 8. Attenuation Error vs. Attenuation
Setting at 10 MHz and 510 MHz
1.5
2
0
1
Error (dB)
-4
Error (dB)
31 dB
0
-6
-8
-10
0
500
1000
1500
2000
2500
3000
LE
H
PE
T
-0.5
-1
10 MHz @ 25 C
510 MHz @ 25 C
10 MHz @ -40 C
510 MHz @ -40 C
10 MHz @ 85 C
510 MHz @ 85 C
10
-1.5
3500
4000
0
5
15
1.5
1
0.5
Error (dB)
0
-0.5
-1
1510 MHz @ 25 C
2010 MHz @ 25 C
1510 MHz @ -40 C
2010 MHz @ -40 C
1510 MHz @ 85 C
2010 MHz @ 85 C
0
5
10
15
-1.5
30
35
43
12
20
25
Attenuation State (dB)
20
25
Attenuation State (dB)
E
30
35
30
35
-2
0.5
Frequency (MHz)
Figure 9. Attenuation Error vs. Attenuation
Setting 1010 MHz and 1210 MHz
1.5
1
0.5
Error (dB)
0
-1.5
EP
LA
0
5
10
15
20
Attenuation State (dB)
O
-1
-0.5
Note: Positive attenuation error indicates higher attenuation than target value
Document No. DOC-30007-2
│
www.psemi.com
R
BS
C
1210 MHZ @ 25 C
1210 MHz @ -40 C
1210 MHz @ 85 C
1010 MHz @ 25 C
1010 MHz @ -40 C
1010 MHz @ 85 C
E
25
W
O
IT
Figure 10. Attenuation Error vs. Attenuation
Setting at
1510
MHz and 2010 MHz
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE4306
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0V unless otherwise noted
Figure 11. Attenuation Error vs. Attenuation
Setting at
2010 MHz and 2510 MHz
1.5
Figure 12. 1 dB Compression vs. Frequency
40
1
35
1 dB Compression (dBm)
0
30
-0.5
-1
-1.5
0
5
10
15
20
25
20
30
35
1000
43
12
1500
2000
2500
Frequency (MHz)
2210 MHz @ 25 C
2510 MHz @ 25 C
2210 MHz @ -40 C
2510 MHz @ -40 C
2210 MHz @ 85 C
2510 MHz @ 85 C
LE
H
PE
T
25
3000
E
0 dB
1 dB
2 dB
31 dB
3000
0.5
Error (dB)
Attenuation State (dB)
Figure 13. Input IP3 vs. Frequency
60
55
50
45
IP3 (dBm)
40
35
30
25
20
O
1 dB
2 dB
4 dB
1000
1500
EP
LA
2000
Frequency (MHz)
Note: Positive attenuation error indicates higher attenuation than target value
R
BS
C
0 dB
E
8 dB
16 dB
31 dB
2500
W
Document No. DOC-30007-2
│
UltraCMOS
®
RFIC Solutions
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
O
IT
PE4306
Product Specification
Figure 14. Pin Configuration (Top View)
GND
N/C
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
Parameter/Conditions
Power supply voltage
Voltage on any DC input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
+30
500
Units
V
V
°C
dBm
V
20
19
18
17
16
C16
RF1
Data
Clock
LE
1
2
3
4
5
10
15
C8
RF2
P/S
Vss/GND
GND
V
I
T
ST
P
IN
V
ESD
20-lead
QFN
4x4 mm
Exposed Solder Pad
14
13
12
11
PUP1
PUP2
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
C16
RF1
Data
Clock
LE
V
DD
PUP1
PUP2
V
DD
GND
GND
Description
Parameter
43
12
Min
2.7
Typ
3.0
Max
3.3
100
0.7xV
DD
0.3xV
DD
1
+24
85
-40
Table 2. Pin Descriptions
LE
H
PE
T
Table 4. Operating Ranges
V
DD
Power Supply
Voltage
I
DD
Power Supply
Current
Digital Input High
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
V
DD
V
DD
GND
E
6
7
8
9
Units
V
μA
V
V
μA
dBm
°C
Attenuation control bit, 16 dB (Note 4)
RF port (Note 1)
Serial interface clock input
Latch Enable input (Note 2)
Power supply pin
Power-up selection bit
Power-up selection bit
Power supply pin
Ground connection
Ground connection
Serial interface data input (Note 4)
BS
C
V
ss
/GND
P/S
C8
C4
C2
C1
Parallel/Serial mode select
RF2
RF port (Note 1)
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Ground connection
Attenuation control bit, 1 dB
GND
N/C
Negative supply voltage or GND connection
(Note 3)
O
Paddle
GND
E
W
No connect. Can be connected to any bias
Notes: 1. Both RF ports must be held at 0 V
DC
or DC blocked with an external
series capacitor
2. Latch Enable (LE) has an internal 100 kΩ resistor to V
DD
3. Connect pin 12 to GND to enable internal negative voltage generator.
Connect pin 12 to V
SS
(-V
DD
) to bypass and disable internal negative
voltage generator
4. Place a 10 kΩ resistor in series, as close to pin as possible to avoid
frequency resonance. See “Resistor on Pin 1 & 3” paragraph
EP
LA
Ground for proper operation
Document No. DOC-30007-2
│
www.psemi.com
R
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the 5x5 mm QFN
package is MSL1.
O
IT
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in
Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Switching Frequency
The PE4306 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see
Figure 16)
will eliminate package resonance between
the RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
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