CY7C09159AV
CY7C09169AV3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
CY7C09159AV
CY7C09169AV
3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 8K x 9 organization (CY7C09159AV)
— 16K x 9 organization (CY7C09169AV)
• Three Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 83-MHz
operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 9 and 12 ns (max.)
• 3.3V Low operating power
— Active = 135 mA (typical)
— Standby = 10
µA
(typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pb-Free packages available
Logic Block Diagram
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
FT/Pipe
L
I/O
0L
−I/O
8L
0/1
1
0
0
1
0/1
FT/Pipe
R
I/O
0R
−I/O
8R
9
9
I/O
Control
13/14
I/O
Control
13/14
A
0
−A
12/13L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
[1]
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
A
0
−A
12/13R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[1]
Notes:
1. A
0
−A
12
for 8K; A
0
−A
13
for 16K.
Cypress Semiconductor Corporation
Document #: 38-06053 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 6, 2005
CY7C09159AV
CY7C09169AV
Functional Description
The CY7C09159AV and CY7C09169AV are high-speed
synchronous CMOS 8K and 16K x 9 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
[2]
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is regis-
tered for decreased cycle time. Clock to data valid t
CD2
= 9 ns
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available t
CD1
= 18 ns after the
address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
LOW- to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple Chip Enables allows easier
banking of multiple chips for depth expansion configurations.
In the pipelined mode, one cycle is required with CE
0
LOW and
CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
2. When simultaneously writing to the same location, final value cannot be guaranteed.
Document #: 38-06053 Rev. *B
Page 2 of 16
CY7C09159AV
CY7C09169AV
Pin Configuration
100-Pin TQFP
(Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
[3]
NC
NC
NC
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
[3]
NC
NC
NC
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
CY7C09169AV (16K x 9)
CY7C09159AV (8K x 9)
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
GND
GND
GND
I/01R
VCC
VCC
NC
Selection Guide
CY7C09159AV
CY7C09169AV
-9
f
MAX2
(Pipelined)
Max Access Time (Clock to Data, Pipelined)
Typical Operating Current I
CC
Typical Standby Current for I
SB1
(Both Ports TTL Level)
Typical Standby Current for I
SB3
(Both Ports CMOS Level)
Note:
3. This pin is NC for CY7C09159AV.
CY7C09159AV
CY7C09169AV
-12
50
12
115
20
10
NC
NC
Unit
MHz
ns
mA
mA
µA
67
9
135
20
10
Document #: 38-06053 Rev. *B
Page 3 of 16
CY7C09159AV
CY7C09169AV
Pin Definitions
Left Port
A
0L
–A
13L
ADS
L
Right Port
A
0R
–A
13R
ADS
R
Description
Address Inputs (A
0
−A
12
for 8K; A
0
−A
13
for 16K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address counter
with data present on the I/O pins.
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted to
their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual-port memory array. For
read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
Latch-Up Current ..................................................... >200 mA
CE
0L
,CE
1L
CLK
L
CNTEN
L
CE
0R
,CE
1R
CLK
R
CNTEN
R
CNTRST
L
I/O
0L
–I/O
8L
OE
L
R/W
L
FT/PIPE
L
GND
NC
V
CC
CNTRST
R
I/O
0R
–I/O
8R
OE
R
R/W
R
FT/PIPE
R
Maximum Ratings
[4]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°
C to +150
°
C
Ambient Temperature with Power Applied ..–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to V
CC
+0.5V
DC Input Voltage......................................–0.5V to V
CC
+0.5V
Operating Range
Range
Commercial
Industrial
[5]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V ± 300 mV
3.3V ± 300 mV
Note:
4. The voltage on any input or I/O pin can not exceed the power pin during power-up
5. Industrial parts are available in CY7C09169AV only.
Document #: 38-06053 Rev. *B
Page 4 of 16
CY7C09159AV
CY7C09169AV
Electrical Characteristics
Over the Operating Range
CY7C09159AV
CY7C09169AV
-9
Parameter
V
OH
V
OL
V
IH
V
IL
I
OZ
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
Description
Output HIGH Voltage (V
CC
= Min., I
OH
= –4.0 mA)
Output LOW Voltage (V
CC
= Min., I
OH
= +4.0 mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Operating Current (V
CC
= Max.,
I
OUT
= 0 mA) Outputs Disabled
Standby Current (Both Ports TTL Level)
[6]
CE
L
& CE
R
≥
V
IH
, f = f
MAX
Standby Current (One Port TTL Level)
[6]
CE
L
| CE
R
≥
V
IH
, f = f
MAX
Standby Current (Both Ports CMOS Level)
[6]
CE
L
& CE
R
≥
V
CC
– 0.2V, f = 0
Standby Current (One Port CMOS Level)
[6]
CE
L
| CE
R
≥
V
IH
, f = f
MAX
Com’l.
Ind.
[5]
Com’l.
Ind.
[5]
Com’l.
Ind.
[5]
Com’l.
Ind.
[5]
Com’l.
Ind.
[5]
85
115
10
500
95
155
20
75
–10
135
2.0
0.8
10
230
–10
115
155
20
30
85
95
10
10
75
85
Min.
2.4
0.4
2.0
0.8
10
180
250
70
80
140
150
500
500
100
110
Typ.
Max.
Min.
2.4
0.4
-12
Typ.
Max.
Unit
V
V
V
V
µA
mA
mA
mA
mA
mA
mA
µA
µA
mA
mA
Capacitance
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 3.3V
Max.
10
10
Unit
pF
pF
AC Test Loads
3.3V
3.3V
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
V
TH
= 1.4V
OUTPUT
C = 30 pF
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 5 pF
R2 = 435Ω
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-state Delay (Load 2)
(Used for t
CKLZ
, t
OLZ
, & t
OHZ
including scope and jig)
Note:
6. CE
L
and CE
R
are internal signals. To select either the left or right port, both CE
0
AND CE
1
must be asserted to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Document #: 38-06053 Rev. *B
Page 5 of 16
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