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SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G − APRIL 1999 − REVISED APRIL 2005
D
Member of the Texas Instruments
D
D
D
D
D
Widebus Family
Designed to Be Used in Voltage-Limiting
Applications
6.5-Ω On-State Connection Between Ports
A and B
Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
Direct Interface With GTL+ Levels
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
description/ordering information
The SN74TVC16222A provides 23 parallel
NMOS pass transistors with a common gate. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device can be used as a 22-bit switch, with the
gates cascaded together to a reference transistor.
The low-voltage side of each pass transistor is
limited to a voltage set by the reference transistor.
This is done to protect components with inputs
that are sensitive to high-state voltage-level
overshoots. (See
Application Information
in this
data sheet.)
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GATE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can
be used as the reference transistor. Because, within the device, the characteristics from transistor to transistor
are equal, the maximum output high-state voltage (V
OH
) is approximately the reference voltage (V
REF
), with
minimal deviation from one output to another. This is a benefit of the TVC solution over discrete devices.
Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the
low-voltage side, and the I/O signals are bidirectional through each FET.
ORDERING INFORMATION
TA
PACKAGE†
Tube
SSOP − DL
−40°C to 85°C
TSSOP − DGG
TVSOP − DGV
Tape and reel
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74TVC16222DL
SN74TVC16222DLR
SN74TVC16222DGGR
SN74TVC16222DGVR
TVC16222A
TVC16222A
TW222A
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2005, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G − APRIL 1999 − REVISED APRIL 2005
simplified schematic
GATE
48
B1
47
B2
46
B3
45
B4
44
B23
25
1
GND
2
A1
3
A2
4
A3
5
A4
24
A23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input/output voltage range, V
I/O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance,
θ
JA
(see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are
observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
VI/O
VGATE
IPASS
TA
Input/output voltage
GATE voltage
Pass-transistor current
Operating free-air temperature
−40
0
0
20
TYP
MAX
5.5
5.5
64
85
UNIT
V
V
mA
°C
application operating conditions (see Figure 3)
MIN
VBIAS
VGATE
VREF
VDPU
IPASS
IREF
TA
BIAS voltage
GATE voltage
Reference voltage
Drain pullup voltage
Pass-transistor current
Reference-transistor current
Operating free-air temperature
−40
VREF + 0.6
VREF + 0.6
0
2.36
TYP
2.1
2.1
1.5
2.5
14
5
85
MAX
5
5
4.4
2.64
20
UNIT
V
V
V
V
mA
µA
°C
2
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G − APRIL 1999 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOL
Ci(GATE)
Cio(off)
Cio(on)
ron‡
VBIAS = 0,
IREF = 5
mA,
VDPU = 2.625 V,
VI = 3 V or 0
VO = 3 V or 0
VO = 3 V or 0
IREF = 5
mA,
VDPU = 2.625 V,
VREF = 1.365 V,
RDPU = 150
Ω
VS = 0.175 V,
See Figure 2
TEST CONDITIONS
II = −18 mA
VREF = 1.365 V,
RDPU = 150
Ω
VS = 0.175 V,
See Figure 2
73
4
12
12
25
12.5
MIN
TYP†
MAX
−1.2
350
UNIT
V
mV
pF
pF
pF
Ω
† All typical values are at TA = 25°C.
‡ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower voltage of the two (A or B) terminals.
electrical characteristics from −40°C to 75°C
PARAMETER
ron‡
IREF = 5
mA,
VDPU = 2.625 V,
TEST CONDITIONS
VREF = 1.552 V,
RDPU = 150
Ω
VS = 0.175 V,
See Figure 2
MIN
MAX
10
UNIT
Ω
‡ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower voltage of the two (A or B) terminals.
switching characteristics over recommended operating
V
DPU
= 2.36 V to 2.64 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
A or B
free-air
temperature
MIN
0
MAX
4
4
range,
UNIT
ns
TO
(OUTPUT)
B or A
0
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DALLAS, TEXAS 75265
3
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G − APRIL 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
3.3 V
Motherboard
Interface
VDPU
200 kΩ
†
RDPU =
150
Ω
B2
46
†
RDPU =
150
Ω
B3
45
†
RDPU =
150
Ω
B4
44
†
RDPU =
150
Ω
B23
25
‡
GATE
48
B1 (VBIAS)
47
TVC16222A
1
2
A1 (VREF)
§
3
A2 (VS)
§
4
A3 (VS)
§
5
A4 (VS)
§
24
A23 (VS)
Open-Drain
Test Interface
TESTER CALIBRATION SETUP (see Note C)
GATE
Input
Tester
tPLHREF
2.5 V
1.25 V
1.25 V
0V
tPHLREF
2.5 V
1.25 V
1.25 V
VOL
tPHLDUT
2.5 V
1.25 V
tPLH
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.25 V
VOL
tPHL
(see Note E)
DEFINITION
Output tested
Output reference
Input tested
SYMBOL
†
‡
§
Output
Reference
tPLHDUT
Output
Device
Under Test
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω,
tr
≤
2 ns, tf
≤
2 ns.
B. The outputs are measured one at a time, with one transition per measurement.
C. Test procedure: tPLHREF and tPHLREF are obtained by measuring the propagation delay of a reference measuring point.
tPLHDUT and tPHLDUT are obtained by measuring the propagation delay of the device under test.
D. tPLH = tPLHDUT − tPLHREF
E. tPHL = tPHLDUT − tPHLREF
Figure 1. Tester Calibration Setup and Voltage Waveforms
4
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•
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