Reference crystal input or external reference clock input.
Reference crystal feedback.
Buffered reference clock output.
Configurable clock output D.
CPU frequency clock output.
Configurable clock output B.
Configurable clock output A.
Configurable clock output F.
CPU clock select input, bit 0.
CPU clock select input, bit 1.
CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
[3]
Places outputs in three-state
[4]
condition and shuts down chip when LOW. Optionally, only
places outputs in three-state
[4]
condition and does not shut down chip when LOW.
Battery supply for 32.768-kHz circuit.
32.768-kHz crystal input.
Notes:
1. For best accuracy, use a parallel-resonant crystal, C
LOAD
≈
17 pF or 18 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.
4. The CY2291 has weak pull-downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
Document #: 38-07189 Rev. *A
Page 2 of 14
CY2291
Operation
The CY2291 is a third-generation family of clock generators.
The CY2291 is upwardly compatible with the industry standard
ICD2023 and ICD2028 and continues their tradition by provid-
ing a high level of customizable features to meet the diverse
clock generation needs of modern motherboards and other
synchronous systems.
All parts provide a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in
any combination. Multiple outputs configured for the same or
related
[3]
frequencies will have low (<500 ps) skew, in effect
providing on-chip buffering for heavily loaded signals.
The CY2291 can be configured for either 5V or 3.3V operation.
The internal ROM tables use EPROM technology, allowing full
customization of output frequencies. The reference oscillator
has been designed for 10-MHz to 25-MHz crystals, providing
additional flexibility. No external components are required with
this crystal. Alternatively, an external reference clock of fre-
quency between 1 MHz and 30 MHz can be used. Customers
using the 32-kHz oscillator should connect a 10-MΩ resistor in
parallel with the 32-kHz crystal.
shutdown is enabled, a LOW on this pin also shuts off the
PLLs, counters, the reference oscillator, and all other active
components. The resulting current on the V
DD
pins will be less
than 50
µA
(for Commercial Temp. or 100
µA
for Industrial
Temp.) plus 15
µA
max. for the 32-kHz subsystem and is typ-
ically 10
µA.
After leaving shutdown mode, the PLLs will have
to re-lock. All outputs except 32K have a weak pull-down so
that the outputs do not float when three-stated.
[4]
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs except 32K can be shut off in nearly any
combination. The only limitation is that if a PLL is shut off, all
outputs derived from it must also be shut off. Suspending a
PLL shuts off all associated logic, while suspending an output
simply forces a three-state condition.
[3]
The CPUCLK can slew (transition) smoothly between 8 MHz
and the maximum output frequency (100 MHz at 5V/80 MHz
at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz
at 3.3V for Industrial Temp. and for field-programmed parts).
This feature is extremely useful in “Green” PC and laptop ap-
plications, where reducing the frequency of operation can re-
sult in considerable power savings. This feature meets all 486
and Pentium® processor slewing requirements.
Output Configuration
The CY2291 has five independent frequency sources on-chip.
These are the 32-kHz oscillator, the reference oscillator, and
three Phase-Locked Loops (PLLs). Each PLL has a specific
function. The System PLL (SPLL) drives the CLKF output and
provides fixed output frequencies on the configurable outputs.
The SPLL offers the most output frequency divider options.
The CPU PLL (CPLL) is controlled by the select inputs
(S0–S2) to provide eight user-selectable frequencies with
smooth slewing between frequencies. The Utility PLL (UPLL)
provides the most accurate clock. It is often used for miscella-
neous frequencies not provided by the other frequency sourc-
es.
All configurations are EPROM programmable, providing short
sample and production lead times. Please refer to the applica-
tion note “Understanding the CY2291, CY2292, and CY2295”
for information on configuring the part.
CyClocks™ Software
CyClocks is an easy-to-use application that allows you to con-
figure any one of the EPROM programmable clocks offered by
Cypress. You may specify the input frequency, PLL and output
frequencies, and different functional options. Please note the
output frequency ranges in this data sheet when specifying
them in CyClocks to ensure that you stay within the limits.
CyClocks also has a power calculation feature that allows you
to see the power consumption of your specific configuration.
You can download a copy of CyClocks for free on Cypress’s
website at www.cypress.com.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Program-
mers is a portable programmer designed to custom program
our family of EPROM Field Programmable Clock Devices. The
FTG programmers connect to a PC serial port and allow users
of CyClocks software to quickly and easily program any of the
CY2291F, CY2292F, CY2071AF, and CY2907F devices. The
ordering code for the Cypress FTG Programmer is CY3670.
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when
pulled LOW (the 32-kHz clock output is not affected). If system
Document #: 38-07189 Rev. *A
Page 3 of 14
CY2291
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Storage Temperature ................................. –65°C to +150°C
Max. Soldering Temperature (10 sec) ..........................260°C
Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
Electrical Characteristics, Commercial 5.0V
Parameter
V
OH
V
OL
V
OH–32
V
OL–32
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
I
BATT
Description
HIGH-Level Output Voltage I
OH
= 4.0 mA
LOW-Level Output Voltage I
OL
= 4.0 mA
32.768-kHz HIGH-Level
Output Voltage
32.768-kHz LOW-Level
Output Voltage
LOW-Level Input Voltage
[9]
Input HIGH Current
Input LOW Current
Output Leakage Current
V
DD
Supply Current
[10]
Commercial
V
DD
Power Supply Current
in Shutdown Mode
[10]
V
BATT
Power Supply
Current
I
OH
= 0.5 mA
I
OL
= 0.5 mA
2.0
0.8
<1
<1
75
10
5
10
10
250
100
50
15
Conditions
Min.
2.4
0.4
V
BATT
0.5
0.4
Typ.
Max.
Unit
V
V
V
V
V
V
µA
µA
µA
mA
µA
µA
HIGH-Level Input Voltage
[9]
Except crystal pins
Except crystal pins
V
IN
= V
DD
–0.5V
V
IN
= +0.5V
Three-state outputs
V
DD
= V
DD
Max., 5V operation
Shutdown active,
excluding V
BATT
V
BATT
= 3.0V
CY2291/CY2291F
Notes:
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is
recommended that a 150Ω pull-up resistor to V
DD
be connected to the Xout pin.
9. Xtal inputs have CMOS thresholds.
10. Load = Max., V
IN
= 0V or V
DD
, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following
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