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PLDM4-3G: 产品描述Active Delay Line, Programmable, 1-Func, 7-Tap, True Output, TTL, PDSO16, SMD-16; 产品类别逻辑逻辑; 文件大小26KB，共1页; 制造商Rhombus Industries, Inc.; 官网地址http://www.rhombus-ind.com/

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PLDM4-3G概述

Active Delay Line, Programmable, 1-Func, 7-Tap, True Output, TTL, PDSO16, SMD-16

PLDM4-3G规格参数

参数名称	属性值
零件包装代码	SOIC
包装说明	SOP,
针数	16
Reach Compliance Code	unknown
JESD-30 代码	R-PDSO-G16
逻辑集成电路类型	ACTIVE DELAY LINE
功能数量	1
抽头/阶步数	7
端子数量	16
最高工作温度	70 °C
最低工作温度
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
可编程延迟线	YES
认证状态	Not Qualified
座面最大高度	7.62 mm
最大供电电压 (Vsup)	5.25 V
最小供电电压 (Vsup)	4.75 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	TTL
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	2.54 mm
端子位置	DUAL
总延迟标称（td）	25 ns
宽度	10.16 mm
Base Number Matches	1

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3-Bit Programmable Delay Modules

PLDM4 Series

FAST/TTL Logic

7 Delay Steps -- 4 ns Inherent Delay

Available in Surface Mount

Electrical Specifications at 25

3-Bit FAST

Part Number

PLDM4-0.5

PLDM4-0.7

PLDM4-0.8

PLDM4-1

PLDM4-1.2

PLDM4-1.25

PLDM4-1.3

PLDM4-1.5

PLDM4-1.8

PLDM4-2

PLDM4-2.5

PLDM4-2.6

PLDM4-3

Delay per

Step (ns)

0.5 ± .25

0.7 ± .30

0.8 ± .30

1.0 ± .4

1.2 ± .4

1.25 ± .5

1.3 ± .5

1.5 ± .5

1.8 ± .6

2.0 ± .7

2.5 ± .7

2.6 ± .7

3.0 ± .7

Error ref.

to 000

(ns)

± .30

± .40

± .50

± .60

± .70

± .80

± .90

± 1.0

Initial

Delay (ns)

000

4 ± 1.0

FAST/TTL 3-Bit Schematic

Vcc

3-Bit Programmable

Delay Line

Output

Buffer

OUT

GND

Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)

000

0.0

001

0.5

0.7

0.8

1.0

1.2

1.25

1.3

1.5

1.8

2.0

2.5

2.6

3.0

010

1.0

1.4

1.6

2.0

2.4

2.50

2.6

3.0

3.6

4.0

5.0

5.2

6.0

011

1.5

2.1

2.4

3.0

3.6

3.75

3.9

4.5

5.4

6.0

7.5

7.8

9.0

100

2.0

2.8

3.2

4.0

4.8

5.00

5.2

6.0

7.2

8.0

10.0

10.4

12.0

101

2.5

3.5

4.0

5.0

6.0

6.25

6.5

7.5

9.0

10.0

12.5

13.0

15.0

110

3.0

4.2

4.8

6.0

7.2

7.50

7.8

9.0

10.8

12.0

15.0

15.6

18.0

111

3.5

4.9

5.6

7.0

8.4

8.75

9.1

10.5

12.6

14.0

17.5

18.2

21.0

CUMULATIVE TOLERANCES:

"Error" Tolerance is for Programmed Delays referenced to Initial Delay, Setting "000."

For example, the setting "111" delay of PLDM4-10 is 70.0

3.0ns ref. to "000," and 74.0

4.0ns referenced to the input.

ENABLE

input (Pin 7) is active low. Output will be disabled ( low) when " E " is high.

INPUT FAN-IN:

Input, pin 4, is loaded by the internal passive

network and 8 gate inputs (74F type). The source driving Pin 4

should be FAST/TTL (74S/74F) type or equivalent, and should not

be used to drive any load other than the delay line input.

Dimensions in Inches (mm)

TEST CONDITIONS

-- FAST / TTL

Supply Voltage ............................................... 5.00VDC

Input Pulse Voltage ................................................... 3.20V

Input Pulse Rise Time ....................................... 3.0 ns max.

Input Pulse Width / Period ........................... 1000 / 2000 ns

1. Measurements made at 25

2. Delay Times measured at 1.50V level of leading edge.

3. Rise Times measured from 0.75V to 2.40V.

4. 10pf probe and fixture load on output.

.810

(20.57)

MAX.

.400

(10.16)

MAX.

.260 .300

(6.60) (7.62)

TYP. MAX.

.120

(3.05)

MIN.

.010

(0.25)

TYP.

.020

(0.51)

TYP.

.050 .100

(1.27) (2.54)

TYP.

.300

(7.62)

OPERATING SPECIFICATIONS

Supply Voltage ................................... 5.00 ± 0.25 VDC

Supply Current .......................... 60 mA typ., 80 mA max

Logic “1” Input *: V

..................... 2.00 V min., 5.50 V max.

............................... 50

µA

max. @ 2.70V

Logic “0” Input *: V

....................................... 0.80 V max.

............................................ -0.6 mA mA

Logic “1” Voltage Out ................................... 2.40 V min.

Logic “0” Voltage Out ................................ 0.50 V max.

Input Pulse Width ............................. 40% of Delay min.

Operating Temperature Range ......................... -0

to +70

Storage Temperature Range ...................... -65

to +150

* Refer to "INPUT FAN-IN" note above.

IIL/IIH specified for Programming pins 9, 10 & 11.

16-Pin SMD Pkg. Unused leads are NOT removed.

To Specify SMD Package, Add "G" Suffix to P/N

Examples: PLDM4-1.25G, PLDM4-2G

1.02

(25.9)

MAX.

.400

(10.16)

.285

(7.24)

MAX.

.010

(0.25)

TYP.

.020

(0.51)

TYP.

.040

(1.02)

TYP.

.100

(2.54)

TYP.

.015

(0.38)

.025

(0.64)

.510 (12.95)

.480 (12.19)

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sales@rhombus-ind.com

TEL: (714) 898-0960

FAX: (714) 896-0971

PLDM4-G 2001-01

PLDM4-3G相似产品对比

	PLDM4-3G	PLDM4-1G	PLDM4-3	PLDM4-2G
描述	Active Delay Line, Programmable, 1-Func, 7-Tap, True Output, TTL, PDSO16, SMD-16	Active Delay Line, Programmable, 1-Func, 7-Tap, True Output, TTL, PDSO16, SMD-16	Active Delay Line, Programmable, 1-Func, 7-Tap, True Output, TTL, PDIP8,	Active Delay Line, Programmable, 1-Func, 7-Tap, True Output, TTL, PDSO16, SMD-16
包装说明	SOP,	SOP,	DIP,	SMD-16
Reach Compliance Code	unknown	unknown	unknown	unknown
JESD-30 代码	R-PDSO-G16	R-PDSO-G16	R-PDIP-T8	R-PDSO-G16
逻辑集成电路类型	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE
功能数量	1	1	1	1
抽头/阶步数	7	7	7	7
端子数量	16	16	8	16
最高工作温度	70 °C	70 °C	70 °C	70 °C
输出极性	TRUE	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SOP	SOP	DIP	SOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE	SMALL OUTLINE	IN-LINE	SMALL OUTLINE
可编程延迟线	YES	YES	YES	YES
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	7.62 mm	7.62 mm	7.62 mm	7.62 mm
最大供电电压 (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V
最小供电电压 (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V
表面贴装	YES	YES	NO	YES
技术	TTL	TTL	TTL	TTL
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING	THROUGH-HOLE	GULL WING
端子节距	2.54 mm	2.54 mm	2.54 mm	2.54 mm
端子位置	DUAL	DUAL	DUAL	DUAL
总延迟标称（td）	25 ns	11 ns	25 ns	18 ns
宽度	10.16 mm	10.16 mm	7.62 mm	10.16 mm
零件包装代码	SOIC	SOIC	-	SOIC
针数	16	16	-	16
Base Number Matches	1	1	1	-

PLDM4-3G

PLDM4-3G概述

PLDM4-3G规格参数

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PLDM4-3G相似产品对比

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