CY7C1302DV25
9-Mbit Burst of Two Pipelined SRAMs
with QDR™ Architecture
9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
Features
■
Functional Description
The CY7C1302DV25 is a 2.5 V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists of
two separate ports to access the memory array. The Read port
has dedicated data outputs to support Read operations and the
Write Port has dedicated data inputs to support Write operations.
Access to each port is accomplished through a common address
bus. The Read address is latched on the rising edge of the
K clock and the Write address is latched on the rising edge of
K clock. QDR has separate data inputs and data outputs to
completely eliminate the need to “turn-around” the data bus
required with common I/O devices. Accesses to the
CY7C1302DV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock (K).
In order to maximize data throughput, both Read and Write ports
are equipped with DDR interfaces. Therefore, data can be
transferred into the device on every rising edge of both input
clocks (K and K) and out of the device on every rising edge of
the output clock (C and C, or K and K in a single clock domain)
thereby maximizing performance while simplifying system
design. Each address location is associated with two 18-bit
words that burst sequentially into or out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click
here.
Separate independent Read and Write data ports
❐
Supports concurrent transactions
167-MHz clock for high bandwidth
❐
2.5 ns Clock-to-Valid access time
2-word burst on all accesses
Double Data Rate (DDR) interfaces on both Read and Write
ports (data transferred at 333 MHz) @ 167 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
Single multiplexed address input bus latches address inputs
for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
2.5 V core power supply with HSTL Inputs and Outputs
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–1.9 V)
JTAG Interface
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Configurations
CY7C1302DV25 – 512 K × 18
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
167 MHz
167
500
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 38-05625 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 28, 2017
CY7C1302DV25
Logic Block Diagram – CY7C1302DV25
D
[17:0]
18
Write
Data Reg
Write Add. Decode
Read Add. Decode
A
(17:0)
Address
Register
18
Write
Data Reg
K
K
CLK
Gen.
256Kx18
Memory
Array
256Kx18
Memory
Array
Address
Register
18
A
(17:0)
Control
Logic
RPS
C
C
Read Data Reg.
36
Vref
WPS
BWS
0
BWS
1
Control
Logic
18
18
Reg.
Reg.
18
Reg. 18
18
Q
[17:0]
Document Number: 38-05625 Rev. *J
Page 2 of 25
CY7C1302DV25
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 6
Single Clock Mode ...................................................... 6
Concurrent Transactions ............................................. 6
Depth Expansion ......................................................... 6
Programmable Impedance .......................................... 7
Application Example ........................................................ 7
Truth Table ........................................................................ 8
Write Cycle Descriptions ................................................. 8
IEEE 1149.1 Serial Boundary Scan (JTAG) .................... 9
Disabling the JTAG Feature ........................................ 9
Test Access Port ......................................................... 9
Performing a TAP Reset ............................................. 9
TAP Registers ............................................................. 9
TAP Instruction Set ..................................................... 9
TAP Controller State Diagram ....................................... 11
TAP Controller Block Diagram ...................................... 12
TAP Electrical Characteristics ...................................... 12
TAP AC Switching Characteristics ............................... 13
TAP Timing and Test Conditions .................................. 14
Identification Register Definitions ................................ 15
Scan Register Sizes ....................................................... 15
Instruction Codes ........................................................... 15
Boundary Scan Order .................................................... 16
Maximum Ratings ........................................................... 17
Operating Range ............................................................. 17
Electrical Characteristics ............................................... 17
DC Electrical Characteristics ..................................... 17
AC Electrical Characteristics ..................................... 17
Thermal Resistance ........................................................ 18
Capacitance .................................................................... 18
AC Test Loads and Waveforms ..................................... 18
Switching Characteristics .............................................. 19
Switching Waveforms .................................................... 20
Read/Write/Deselect Sequence ................................ 20
Ordering Information ...................................................... 21
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC®Solutions ....................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 38-05625 Rev. *J
Page 3 of 25
CY7C1302DV25
Pin Configurations
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1302DV25 (512K × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
2
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
3
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
5
BWS
1
NC
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
6
K
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
C
7
NC
BWS
0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Gnd/144M NC/36M
NC/18M Gnd/72M
Document Number: 38-05625 Rev. *J
Page 4 of 25
CY7C1302DV25
Pin Definitions
Name
D
[17:0]
WPS
I/O
Description
Input-
Data input signals, sampled on the rising edge of K and K clocks during valid Write operations.
Synchronous
Input-
Write Port Select, active LOW.
Sampled on the rising edge of the K clock. When asserted active, a
Synchronous Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause
D
[17:0]
to be ignored.
Input-
Byte Write Select 0, 1, active LOW.
Sampled on the rising edge of the K and K clocks during Write
Synchronous operations. Used to select which byte is written into the device during the current portion of the Write
operations. Bytes not written remain unaltered.
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
will cause the corresponding byte of data to be ignored and not written into the device.
Input-
Address Inputs.
Sampled on the rising edge of the K (read address) and K (write address) clocks for
Synchronous active Read and Write operations. These address inputs are multiplexed for both Read and Write
operations. Internally, the device is organized as 512 K × 18 (2 arrays each of 256 K × 18). These inputs
are ignored when the appropriate port is deselected.
Outputs-
Data Output signals.
These pins drive out the requested data during a Read operation. Valid data is
Synchronous driven out on the rising edge of both the C and C clocks during Read operations or K and K when in
single clock mode. When the Read port is deselected, Q
[17:0]
are automatically three-stated.
Input-
Read Port Select, active LOW.
Sampled on the rising edge of positive input clock (K). When active, a
Synchronous Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected,
the pending access is allowed to complete and the output drivers are automatically three-stated following
the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers.
Input-Clock
Positive Input Clock for Output Data.
C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
Negative Input Clock for Output Data.
C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
cack to the controller. See application example for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[17:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the device
and to drive out data through Q
[17:0]
when in single clock mode.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data
bus impedance. Q
[17:0]
output impedance is set to 0.2 × RQ, where RQ is a resistor connected between
ZQ and ground. Alternately, this pin can be connected directly to V
DDQ
, which enables the minimum
impedance mode. This pin cannot be connected directly to GND or left unconnected.
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Address expansion for 18M.
This is not connected to the die and so can be tied to any voltage level.
Address expansion for 36M.
This is not connected to the die and so can be tied to any voltage level.
Address expansion for 72M.
This must be tied LOW.
Address expansion for 144M.
This must be tied LOW.
Not connected to the die.
Can be tied to any voltage level.
BWS
0
,
BWS
1
A
Q
[17:0]
RPS
C
C
Input-Clock
K
Input-Clock
K
ZQ
Input-Clock
Input
TDO
TCK
TDI
TMS
NC/18M
NC/36M
GND/72M
GND/144M
NC
Output
Input
Input
Input
N/A
N/A
Input
Input
N/A
Document Number: 38-05625 Rev. *J
Page 5 of 25
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