UM6522/A
Versatile Interface Adap ter( VIA)
Features
. Two Shit bi-directional I/O ports
n
Two 16-bit programmable timer/counters
m Serial data port
n
Single +5V power supply
m TTL compatible except Port A
n
CMOS compatible peripheral Port A lines
m Expanded “handshake” capability allows positive
control of data transfers between processor and periph-
eral devices
n
Latched input and output registers
n
1 MHz and 2 MHz Operation
General Description
The UM6522/A Versatile Interface Adapter (VIA) is a very
flexible l/O control device. In addition, this device con-
tains a pair of very powerful 16.bit interval timers, a serlal-
to-parallel/parallel-to-serial shift register and input data
latching on the peripheral ports. Expanded handshaking
capability allows control of bi-directional data transfers
between VIA’s in multiple processor Systems.
Control of peripheral devices is handled primarily through
two Shit bi-directional ports. Esch line tan be program-
med as either an input or- an output. Several peripheral
l/O lines tan be controlled directly from the interval timers
for generating programmable frequency Square waves or
for counting externally generated Pulses.
To facilitate
control of the many powerful features of this Chip, an
interrupt flag register, an interrupt enable register and a
pair of function control registers are provided.
Pin Configuration
Block Diagram
“SS c
PA0 c
PA1 c
2
3
39
38
37
36
35
34
33
2
8
E
$
;:
30
29
28
27
26
25
24
23
22
21
PA2 r 4
PA3 c 5
PA4 c 6
PA5 c 7
PA6 c 8
PA7 [z
PB0 c
PB1 c
9
‘O
11
13
14
15
16
17
16
19
20
] CA1
] CA2
-J RSO
] RSl
] RS2
] RS3
]RES
1 DO
1 D’
1
D2
I] D3
2 D4
7 D5
7
PB2 [ ‘12
PB3 [
PB4 c
PB5 [
D6
7 07
7 $2
7 CS1
Jcs2
PB6 c
PB7 [I
CB1 c
CB2 c
“cc c
5-18
GD
UMC
“Comments
UM6522/A
+8.0 VOLTS
.
1
+4v
to
+7v
GND-2.0V to 0.5V
GND-0.5V to Vcc +0.5V
-65°c
to
+1 5o”c
.
. oOc
to
+70°c
. . . . . ...<...<
1 Watt
Absolute Maximum Ratings”
Supply Voltage . . . .
Operating Voltage Range .
Input Voitage Applied
I/O P i n V o l t a g e A p p l i e d
Storage Temperature Range
Operating Temperature Range
Maximum Power Dissipation
.
Stresses above those listed under “Absolute Maximum
Ratings” may Cause permanent darnage to the device.
These are stress ratings only.
Functional Operation of
this device at these or any other conditions above those in-
dicated in the operational sections of this specification is
not implied and exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
DC Electrical Characteristics
(Vcc = 5.OV * 5%, TA = 0 - 70°C unless otherwise noted)
25°C.
f = 1 MHz
SO, RSl , RSZ, RS3, CSl, CS2,
-PA7, CAl, CAZ, PBO-PB7)
Test Load
PIN-
PIN
1OOpF
1
zz
1
=
OPEN
COLLECTOR
OUTPUT TEST LOAD
-
C= 13OpF MAX. FOR DO-D7
C = 30 pF MAX. FOR ALL OTHER OUTPUTS
Figure 2. Test Load (for all Dynamit Parameters)
5-19
UM6522/A
Read Timing Characteristics (Figure 3.)
Note: tr, tf = 10 to 30ns.
CHIP SELECTS,
R E G I S T E R
SELECTS.
Rm
PERIPHERAL
DATA
DATA BUS
Figure 3. Read Timing Characteristics
Write Timing Characteristics (Figure 4.)
Symbol
TCY
Parameter
Cycle Time
$2 Pulse Width
Address Set-Up Time
Address Hold Time
R/W Set-Up Time
Rm Hold Time
Data Bus Set- Up Time
Data Bus Hold Time
Peripheral Data Delay Time
Peripheral Data Delay Time
to CMOS Levels
UM6522
Min.
1
0.44
180
0
180
0
300
10
-
-
-
-
-
1.0
2.0
I
)
Max.
50
25
-
I
lJMS22A
.
- - .--- --.
Min.
0.50
0.22
90
0
90
0
Max.
50
;!5
1
I
I
Unit
PS
TC
TACW
TCAW
TWGW
TCWW
TDCW
THW
TCFW
TCMOS
I
T
-
-
-
-
PS
ns
ns
ns
ns
ns
ns
PS
PS
q
Note: tr, tf = 10 to 30ns.
E
150
10
-
-
-
1 .o
2.0
&Y CLOCK
CHIP SELECTS.
REGISTER SELECTS.
DATA BUS
PERIPHERAL
DATA
Figure 4. Weite Timing Characteristics
5-20
UiWSSZZ/A
Peripheral Interface Characteristics
T
SR
1
TSRZ
Shlft-Out Delay Time - Time from r& Falling Edge
to CB2, Data Out
Shift-in Setup Time - Time from CB2 Data in to G2
R ising Edge
External Shift Glock (CBl) Setup Time Relative to
& Trailing Edge
Pulse Width - PB6 Input Pulse
Pulse Width - CB1 Input Glock
Pulse Spacing - PB6 Input Pulse
Pulse Spacing - CB1 Input Pulse
CAl, CB1 Set-Up Prior to Transition to Arm Latch
Peripheral Data Hold After CAl, CB1 Transition
Set-Up Required on CAl, CBl, CA2 or CB2 Prior tc
’
Trictqering Edge
Shift Register Glock - Delay from $2
to CB1 Rising Edge
to CB1 Falling Edge
300
100
2 x Tcy
2
xTCY
300
-
TCY
-
-
-
-
I
I
“C
II.3
ns
ns
Lf
1”’
33
59
5i
5h
Tm3
TIPW
TICW
T
IPS
2xTCy
2 x Tcy
TC +50
150
I
TICS
TAI
+---+++
ns
[
1
I
5h
5e
1 5i
ns
I
I
1
ns
1
.
‘-PDH
-
TPWI
l
T,,,I
IC Ta”
_
I
TDPR
TDPL
200
125
ns
ns
5k
5k
Timing Waveforms
READ IRA
OPERATION
c
CA2
“DATA TAKEN”
Figure 5a. CA2 Timing for Read Handshake, Pulse Mode
5-21
UM6522/A
Timing Waveforms (Continued)
-
READ IRA
OPERATION
CA2
“DATA TAKEN”
CA1
“DATA
READY”
Figure 5b. CA2 Timing for Read Handshake, Handshake Mode
$2
ft
-TWHS
-
-TRS~
-
WRITE ORA, ORB
OPERATION
CA2, CB2
“DATA READY”
PA, PB
PERIPHERAL DATA
Figure 5c. CA2, CB2 Timing for Write Handshake, Pulse Mode
WRITE ORA, ORB
OPERATION
CA2, CB2
“DATA READY”
PA, PB
PERIPHERAL DATA
- TWHS-
ATRs~
CAl, CE1
“DATA TAKEN”
ACTIVE
TRANSITION ~
/ ji-
Figure 5d. CA2, CB2 Timing for Write Handshake, Handshake Mode
PA, PB
PERIPHERAL
INPUT DATA
CAl, CB1
INPUT LATCHING
CONTROL
TRANSITION
Figure 5e. Peripheral Data Input Latch Timing
5-22
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