Si5365
P
R E L I M I N A R Y
D
A TA
S
H E E T
P
IN
-P
ROGRAMMABLE
P
RECISION
C
LOCK
M
ULTIPLIER
Description
The Si5365 is a low jitter, precision clock multiplier for
high-speed communication systems, including SONET
OC-48/OC-192, Ethernet, and Fibre Channel, in which
the application requires clock multiplication without
jitter attenuation. The Si5365 accepts four clock inputs
ranging from 19.44 to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 19.44
to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of
popular SONET, Ethernet, and Fibre Channel rates.
The Si5365 is based on Silicon Laboratories' 3rd-
generation DSPLL
®
technology, which provides any-
rate frequency synthesis in a highly integrated PLL
solution that eliminates the need for external VCXO
and loop filter components. The DSPLL loop bandwidth
is digitally programmable, providing jitter performance
optimization at the application level. Operating from a
single 1.8 or 2.5 V supply, the Si5365 is ideal for
providing clock multiplication in high performance
timing applications.
Features
Selectable output frequencies ranging from 19.44 to
1050 MHz
Low jitter clock outputs w/jitter generation as low as
0.6 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(30 kHz to 1.3 MHz)
Four clock inputs w/manual or automatically
controlled hitless switching
Five clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
LOS alarm outputs
Digitally-controlled output phase adjust
Pin-programmable settings
On-chip voltage regulator for 1.8 or 2.5 V ±10%
operation
Small size: 14 x 14 mm 100-pin TQFP
Pb-free, RoHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 line cards
Test and measurement
CKIN1
CKIN2
CKIN3
CKIN4
÷ N31
÷ N32
÷ N33
÷ N34
÷ N2
÷ NC3
CKOUT3
÷ NC1
CKOUT1
DSPLL
®
÷ NC2
CKOUT2
Divider Select
Manual/Auto Switch
Clock Select
LOS/FOS Alarms
Frequency Select
Bandwidth Select
Control
÷ NC5
CKOUT5
VDD (1.8 or 2.5 V)
GND
÷ NC4
CKOUT4
Preliminary Rev. 0.34 3/07
Copyright © 2007 by Silicon Laboratories
Si5365
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5365
Table 1. Performance Specifications
(V
DD
= 1.8 or 2.5 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Supply Current
Symbol
T
A
V
DD
I
DD
Test Condition
Min
–40
2.25
1.62
Typ
25
2.5
1.8
394
Max
85
2.75
1.98
435
Unit
ºC
V
V
mA
f
OUT
= 622.08 MHz
All CKOUTs enabled
LVPECL format output
Only CKOUT1 enabled
f
OUT
= 19.44 MHz
All CKOUTs enabled
CMOS format output
Only CKOUT1 enabled
Tristate/Sleep Mode
—
—
—
253
278
284
321
mA
mA
—
—
19.44
229
TBD
—
261
TBD
707.35
mA
mA
MHz
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CKIN4)
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4,
CKOUT5)
CK
F
CK
OF
Input frequency and clock
multiplication ratio pin-
selectable from table of val-
ues using FRQSEL and
FRQTBL settings. Consult
Silicon Laboratories configu-
ration software DSPLLsim or
Any-Rate Precision Clock
Family Reference Manual at
www.silabs.com/timing
for
table selections.
19.44
—
1049.76
MHz
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing
Common Mode Voltage
Rise/Fall Time
Duty Cycle
CKN
DPP
CKN
VCM
CKN
TRF
CKN
DC
1.8 V ±10%
2.5 V ±10%
20–80%
Whichever is less
0.25
0.9
1.0
—
40
50
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5)
Common Mode
Differential Output Swing
Single Ended Output
Swing
Rise/Fall Time
V
OCM
V
OD
V
SE
CKO
TRF
LVPECL
100
Ω
load
line-to-line
V
DD
– 1.42
1.1
0.5
—
—
—
—
230
V
DD
– 1.25
1.9
0.93
350
V
V
V
ps
—
—
—
—
—
—
1.9
1.4
1.7
11
60
—
V
PP
V
V
ns
%
ns
20–80%
Note:
For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from
www.silabs.com/timing.
2
Preliminary Rev. 0.34
Si5365
Table 1. Performance Specifications (Continued)
(V
DD
= 1.8 or 2.5 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Duty Cycle
PLL Performance
Jitter Generation
Symbol
CKO
DC
J
GEN
Test Condition
Min
45
Typ
—
0.6
Max
55
TBD
Unit
%
ps rms
f
OUT
= 622.08 MHz,
LVPECL output format
50 kHz–80 MHz
12 kHz–20 MHz
—
—
—
0.6
0.05
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps rms
dB
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc
Jitter Transfer
Phase Noise
J
PK
CKO
PN
f
OUT
= 622.08 MHz
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
—
—
—
—
—
—
—
Subharmonic Noise
Spurious Noise
Package
Thermal Resistance
Junction to Ambient
SP
SUBH
SP
SPUR
Phase Noise @ 100 kHz
Offset
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
Still Air
θ
JA
—
40
—
ºC/W
Note:
For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from
www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter
DC Supply Voltage
LVCMOS Input Voltage
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ)
ESD MM Tolerance
Latch-Up Tolerance
Symbol
V
DD
V
DIG
T
JCT
T
STG
Value
–0.5 to 2.75
–0.3 to (V
DD
+ 0.3)
–55 to 150
–55 to 150
2
200
JESD78 Compliant
Unit
V
V
ºC
ºC
kV
V
Note:
Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.34
3
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