Si5315
S
Y N C H R O N O U S
E
T H E R N E T
/ T
E LE C O M
J
I T T E R
A
T T E N U A T I N G
C
L O C K
M
U L T I PL I E R
Features
Provides jitter attenuation and frequency
translation between SONET/PDH and
Ethernet
Supports ITU-T G.8262 Synchronous
Ethernet equipment slave clock (EEC
option 1 and 2) requirements with
optional Stratum 3 compliant timing card
clock source
Two clock inputs/two clock outputs
Input frequency range: 8 kHz–644 MHz
Output frequency range: 8 kHz–644 MHz
Ultra low jitter:
0.23 ps RMS (1.875–20 MHz)
0.47 ps RMS (12 kHz–20 MHz)
Simple pin control interface
Selectable loop bandwidth for jitter
attenuation: 60 to 8.4 kHz
Automatic/Manual hitless switching
and holdover during loss of inputs
clock
Programmable output clock signal
format: LVPECL, LVDS, CML or
CMOS
40 MHz crystal or XO reference
Single supply: 1.8, 2.5, or 3.3 V
On-chip voltage regulator with high
PSRR
Loss of lock and loss of signal alarms
Small size: 6 x 6 mm, 36-QFN
Wide temperature range: –40 to
+85 ºC
Ordering Information:
See page 48.
Applications
CKOUT1–
CKIN1–
CKOUT2+
CKOUT2–
Description
The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous
Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE
EEC options 1 and 2 when paired with a timing card that implements the required
wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to
644.53 MHz. The input clock frequency and clock multiplication ratio are selectable
from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon
Laboratories' third-generation DSPLL
®
technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop bandwidth is
user programmable, providing jitter performance optimization at the application level.
RST 1
FRQTBL 2
LOS1 3
LOS2 4
VDD 5
XA 6
XB
7
36 35 34 33 32 31 30 29 28
27 FRQSEL3
26 FRQSEL2
25 FRQSEL1
NC
GND
CKOUT1+
24 FRQSEL0
23 BWSEL1
22 BWSEL0
21 CS_CA
20 GND
19 GND
LOL
SFOUT0
GND
Pad
GND 8
AUTOSEL 9
10 11 12 13 14 15 16 17 18
CKIN2+
XTAL/CLOCK
DBL2_BY
CKIN1+
CKIN2–
GND
VDD
Functional Block Diagram
XTAL/Clock
Si5315
Clock In 1
DSPLL
Clock In 2
®
Clock Out 1
Output Signal Format[1:0]
Clock Out 2
Loss of Lock
Loss of Signal 1
Loss of Signal 2
Clock 2 Disable/PLL Bypass
Status/Control
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency Select[3:0]
Frequency Table Select
Loop Bandwidth Select[1:0]
Manual/Auto Clock Selection
Clock Switch/Clock Active Indicator
XTAL/Clock
Rev. 1.0 4/12
Copyright © 2012 by Silicon Laboratories
SFOUT1
Synchronous Ethernet line cards
SONET OC-3/12/48 line cards
PON OLT/ONU
Carrier Ethernet switches routers
MSAN / DSLAM
T1/E1/DS3/E3 line cards
Pin Assignments
VDD
Si5315
Si5315
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . .11
1.2. Three-Level (3L) Input Pins (With External Resistors) . . . . . . . . . . . . . . . . . . . . . . . 12
2. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. System Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1. Frequency Multiplication Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3. Input Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5. Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1. Input Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2. Output Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
7.1. Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
8. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
9.1. 10G LAN SyncE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10. Pin Descriptions: Si5315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
11. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
13. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
14.1. Si5315 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Rev. 1.0
3
Si5315
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
ºC
V
V
V
3.3 V nominal
2.5 V nominal
1.8 V nominal
2.97
2.25
1.71
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Supply Current (Supply
current is independent of
V
DD
)
Symbol
I
DD
Test Condition
LVPECL Format
644.53125 MHz Out
All CKOUTs Enabled
1
LVPECL Format
644.53125 MHz Out
Only 1 CKOUT Enabled
1
CMOS Format
25.00 MHz Out
All CKOUTs Enabled
2
CMOS Format
25.00 MHz Out
Only CKOUT1 Enabled
2
Min
—
Typ
251
Max
279
Units
mA
—
217
243
mA
—
204
234
mA
—
194
220
mA
CKINn Input Pins
Input Common Mode Voltage
(Input Threshold Voltage)
V
ICM
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Input Resistance
Input Voltage Level Limits
CKN
RIN
CKN
VIN
Single-ended
0.9
1.0
1.1
20
0
—
—
—
40
—
1.4
1.7
1.95
60
V
DD
V
V
V
k
V
Notes:
1.
Refers to Si5315A speed grade.
2.
Refers to Si5315B speed grade.
3.
This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
4
Rev. 1.0
Si5315
Table 2. DC Characteristics (Continued)
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Single-ended Input Voltage
Swing
Symbol
V
ISE
Test Condition
f
CKIN
< 212.5 MHz
See Figure 2.
f
CKIN
> 212.5 MHz
See Figure 2.
Min
0.2
0.25
0.2
0.25
Typ
—
—
—
—
Max
—
—
—
—
Units
V
PP
V
PP
V
PP
V
PP
Differential Input
Voltage Swing
V
ID
f
CKIN
< 212.5 MHz
See Figure 2.
f
CKIN
> 212.5 MHz
See Figure 2.
CKOUTn Output Clocks
Common Mode
Differential Output Swing
Single Ended Output Swing
Differential Output Voltage
Common Mode
Output Voltage
Differential
Output Voltage
V
OCM
V
OD
V
SE
CKO
VD
CKO
VCM
CKO
VD
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
CML 100
load
line-to-line
CML 100
load
line-to-line
LVDS 100
load
line-to-line
Low swing LVDS 100
load
line-to-line
Common Mode
Output Voltage
Differential Output Resistance
Output Voltage Low
Output Voltage High
CKO
VCM
CKO
RD
CKO
VOLLH
CKO
VOHLH
LVDS 100
load
line-to-line
CML, LVPECL, LVDS,
Disable
CMOS
V
DD
= 1.71 V
CMOS
V
DD
–
1.42
1.1
0.5
350
—
500
350
1.125
—
—
0.8 x V
DD
—
—
—
425
V
DD
–
0.36
700
425
1.2
200
—
—
V
DD
–
1.25
1.9
0.93
500
—
900
500
1.275
—
0.4
—
V
V
PP
V
PP
mV
PP
V
mV
PP
mV
PP
V
V
V
Notes:
1.
Refers to Si5315A speed grade.
2.
Refers to Si5315B speed grade.
3.
This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
Rev. 1.0
5
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