Voltage on any other Pin. . . . . . . . . . . . . . . . . . . . . . . . . V
CC
± 0.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
All typical values are for +25°C ambient temperature and 5V at pin V
CC
. Maximum and minimum specifications
are over the recommended operating conditions. All voltages are referred to the voltage at pin V
SS
. Bit 7 in
control register 0 is “1”, while other bits in control registers are “0”. 400kHz TTL input at SCL. SDA pulled to V
CC
through an external 2kΩ resistor. 2-wire interface in “standby” (Notes 2 and 3 ). WP, A0, A1, and A2 floating.
SYMBOL
Iccstby
Iccfull
PARAMETER
Standby Current Into V
CC
Pin
Full Operation Current Into V
CC
Pin
TEST CONDITIONS
I
OUT
floating, sink mode
2-wire interface reading from
memory, Iout connected to V
SS
, DAC
input bytes: FFh
MIN
TYP
MAX
2
6
UNIT
mA
mA
Iccwrite
Nonvolatile Write Current Into V
CC
Pin Average from START condition until t
WP
after the STOP condition
WP: Vcc, Iout floating, sink mode
VRef unloaded.
On-chip Pull Down Current At Wp, A0, V(WP), V(A0), V(A1), and V(A2) from
A1,and A2
0V to Vcc
Scl And Sda, Input Low
Voltage
Scl And Sda, Input High
Voltage
Scl And Sda Input Current
Sda Output Low Voltage
Sda Output High Current
Wp, A0, A1, And A2 Input Low Voltage
Wp, A0, A1, And A2 Input High
Voltage
Temperature Sensor Range
Temperature Sensor Accuracy
Power-on Reset Threshold Voltage
V
CC
Ramp Rate
Adc Enable Minimum Voltage
(Figure 8)
1.5
0.2
2.6
(Note 7)
Pin voltage between 0 and V
CC
, and
SDA as an input.
I(SDA) = 2 mA
V(SDA) = V
CC
2.0
-1
0
0
0
0.8 x V
CC
-40
0
4
mA
I
PLDN
V
ILTTL
V
IHTTL
I
INTTL
V
OLSDA
I
OHSDA
V
ILCMOS
V
IHCMOS
TSenseRange
TSenseAccuracy
V
POR
VccRamp
V
ADCOK
NOTES:
1
20
0.8
µA
V
V
10
0.4
100
0.2 x V
CC
V
CC
100
±2
2.8
50
2.8
µA
V
µA
V
V
°C
°C
V
mV/µs
V
2. The device goes into Standby: 200 ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby t
WC
after a STOP
that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address
Byte.
3. t
WC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
4. This parameter is periodically sampled and not 100% tested.
3
FN8215.2
February 25, 2008
X96011
D/A Converter Characteristics
(See pg. 5 for standard conditions)
SYMBOL
IFS
Offset
DAC
FSError
DAC
DNL
DAC
INL
DAC
PARAMETER
Iout Full Scale Current
Iout D/a Converter Offset Error
Iout D/a Converter Full Scale Error
Iout D/a Converter
Differential Nonlinearity
Iout D/a Converter Integral
Nonlinearity With Respect To A Straight Line
Through 0 And The Full Scale Value
I1 Sink Voltage Compliance
I1 Source Voltage Compliance
I1 Overshoot On D/a Converter Data Byte
Transition
I1 Undershoot On D/a Converter Data Byte
Transition
I1 Rise Time On D/a Converter Data Byte
Transition; 10% To 90%
Temperature Coefficient Of Output
Current Iout
See Figure 5
In this range the current at I1 vary < 1%
In this range the current at I1 vary < 1%
DAC input byte changing from 00h to
FFh and vice versa, V(I1) is V
CC
- 1.2V
in source mode and 1.2V in sink mode.
(Note 7)
5
±200
TEST CONDITIONS
DAC input Byte = FFh,
Source or sink mode, V(I
OUT
) is
V
CC
-1.2V in source mode and 1.2V in
sink mode.
(Notes 5, 6 )
MIN
1.56
1
-2
-0.5
-1
TYP
1.58
MAX
1.6
1
2
0.5
1
UNIT
mA
LSB
LSB
LSB
LSB
VISink
VISource
I
OVER
I
UNDER
t
rDAC
TCO
I1I2
NOTES:
1.2
0
V
CC
V
CC
- 1.2
0
0
30
V
V
µA
µA
µs
ppm/°C
5. LSB is defined as
[
2 x V(VRef)
]
divided by the resistance between R
255
3
1
or R
2
to Vss.
6. Offset
DAC
: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed
in LSB.
FSError
DAC
: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is
expressed in LSB. The Offset
DAC
is subtracted from the measured value before calculating FSError
DAC
.
DNL
DAC
: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in the output
of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error
before calculating DNL
DAC
.
INL
DAC
: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the
measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
7. These parameters are periodically sampled and not 100% tested.
2-Wire Interface AC Characteristics
SYMBOL
f
SCL
PARAMETER
Scl Clock Frequency
TEST CONDITIONS
See Table 2-Wire Interface Test
Conditions on page 5
(Figure 1, 2 and 3)
t
IN
(Note 11)
t
AA
(Note 11)
t
BUF
(Note 11)
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
Pulse Width Suppression Time At
Inputs
Scl Low To Sda Data Out Valid
Time The Bus Free Before Start Of New
Transmission
Clock Low Time
Clock High Time
Start Condition Setup Time
Start Condition Hold Time
1300
1.3
0.6
600
600
1200
(Note 10)
1200
(Note 10)
50
900
ns
ns
ns
µs
µs
ns
ns
MIN
1 (Note 10)
TYP
MAX
400
UNITS
kHz
4
FN8215.2
February 25, 2008
X96011
2-Wire Interface AC Characteristics
(Continued)
SYMBOL
t
SU:DAT
PARAMETER
Data In Setup Time
TEST CONDITIONS
See Table 2-Wire Interface Test
Conditions on page 5
(Figure 1, 2 and 3)
t
HD:DAT
t
SU:STO
t
DH
t
R
(Note 11)
t
F
(Note 11)
t
SU:WP
(Note 11)
t
HD:WP
(Note 11)
Cb
(Note 11)
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
Sda And Scl Rise Time
Sda And Scl Fall Time
Wp Setup Time
Wp Hold Time
Capacitive Load For Each Bus Line
0
600
50
20 + 0.1Cb
(Note 8)
20 + 0.1Cb
(Note 8)
600
600
400
300
300
µs
ns
ns
ns
ns
ns
ns
pF
MIN
100
TYP
MAX
UNITS
ns
2-Wire Interface Test Conditions
Input Pulse Levels
Input Rise and Fall Times, between 10% and 90%
Input and Output Timing Threshold Level
External Load at pin SDA
10% to 90% of V
CC
10ns
1.4V
2.3kΩ to V
CC
and 100pF to V
SS
Nonvolatile WRITE Cycle Timing
SYMBOL
t
WC
(Note 9)
NOTES:
8. Cb = total capacitance of one bus line (SDA or SCL) in pF.
9. t
WC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
10. The minimum frequency requirement applies between a START and a STOP condition.
11. These parameters are periodically sampled and not 100% tested.
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