DRAM MODULE
KMM372E320(8)0CK
Buffered 32Mx72 DIMM
(16Mx4 base)
Revision 0.0
June 1999
DRAM MODULE
Revision History
Version 0.0 (June 1999)
• The 4th. generation of 64Mb DRAM components are applied for this module.
KMM372E320(8)0CK
DRAM MODULE
KMM372E320(8)0CK
KMM372E320(8)0CK EDO Mode
32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM372E320(8)0C is a 32Mx72bits Dynamic
RAM high density memory module. The Samsung
KMM372E320(8)0C consists of thirty-six CMOS 16Mx4bits
DRAMs in SOJ 400mil packages and two 16 bits driver IC in
TSSOP package mounted on a 168-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on the
printed circuit board for each DRAM. The KMM372E320(8)0C
is a Dual In-line Memory Module and is intended for mounting
into 168 pin edge connector sockets.
FEATURES
• Part Identification
Part number
KMM372E3200CK
KMM372E3280CK
PKG
SOJ
SOJ
Ref.
4K
8K
CBR Ref.
4K/64ms
ROR Ref.
8K/64ms
4K/64ms
• Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single 5V±10% power supply
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
18ns
20ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
• PCB : Height(2000mil), double sided component
PIN CONFIGURATIONS
Pin Front Pin Front Pin Front Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
RSVD
RSVD
V
CC
W0
CAS0
29 *CAS2 57
30 RAS0 58
31
OE0 59
60
32
V
SS
61
33
A0
62
34
A2
63
35
A4
64
36
A6
65
37
A8
66
38
A10
67
39
A12
68
40
V
CC
41 RFU 69
42 RFU 70
43
V
SS
71
44
OE2 72
45 RAS2 73
46 CAS4 74
47 *CAS6 75
76
48
W2
77
49
V
CC
50 RSVD 78
51 RSVD 79
52 DQ18 80
53 DQ19 81
82
54
V
SS
55 DQ20 83
56 DQ21 84
DQ22
DQ23
V
CC
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
DQ35
V
SS
PD1
PD3
PD5
PD7
ID0
V
CC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
DQ53
V
SS
RSVD
RSVD
V
CC
RFU
CAS1
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
*CAS3
RAS1
RFU
V
SS
A1
A3
A5
A7
A9
A11
*A13
V
CC
RFU
B0
V
SS
RFU
RAS3
CAS5
*CAS7
PDE
V
CC
RSVD
RSVD
DQ54
DQ55
V
SS
DQ56
DQ57
Pin Back
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ58
DQ59
V
CC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2
PD4
PD6
PD8
ID1
V
CC
PIN NAMES
Pin Names
A0, B0, A1 - A11
A0, B0, A1 - A12
DQ0 - DQ71
W0, W2
OE0, OE2
RAS0 - RAS3
CAS0, 1,4,5
V
CC
V
SS
NC
PDE
PD1 - 8
ID0 - 1
RSVD
RFU
Function
Address Input(4K ref.)
Address Input(8K ref.)
Data In/Out
Read/Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power(+5V)
Ground
No Connection
Presence Detect Enable
Presence Detect
ID bit
Reserved Use
Reserved for Future Use
Pins marked
′
*
′
are not used in this module.
PD & ID Table
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
ID0
ID1
50NS
1
0
0
0
1
0
0
0
0
0
60NS
1
0
0
0
1
1
1
0
0
0
NOTE : A12 is used for only KMM372E3280CK (8K Ref.)
PD Note :PD & ID Terminals must each be pulled up through a resistor to V
CC
at the next higher
level assembly. PDs will be either open (NC) or driven to V
SS
via on-board buffer circuits.
PD : 0 for Vol of Drive IC & 1 for N.C
ID Note : IDs will be either open (NC) or connected directly to V
SS
without a buffer.
ID : 0 for Vss & 1 for N.C
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS0
CAS0
OE0
W0
A0
A1-A11(A12)
U0
KMM372E320(8)0CK
RAS3
CAS5
OE2
W2
B0
A1-A11(A12)
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U27
RAS1
CAS1
RAS2
CAS4
DQ0-35
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U18
U9
DQ36-71
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U1
U19
U10
U28
U2
U20
U11
U29
U3
U21
U12
U30
U4
U22
U13
U31
U5
U23
U14
U32
U6
U24
U15
U33
U7
U25
U16
U34
U8
U26
U17
U35
NOTE : A12 is used for only KMM372E3280CK(8K Ref.)
Vcc
0.1 or 0.22uF Capacitor
under each DRAM
Vss
To all DRAMs
A0
B0
A1-A11(A12)
W0, OE0
W2, OE2
U0-U8, U18-U26
U9-U17, U27-U35
U0-U35
U0-U8, U18-U26
U9-U17, U27-U35
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
KMM372E320(8)0CK
Rating
-1 to +7.0
-1 to +7.0
-55 to +125
36
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC*1
0.8
Unit
V
V
V
V
*1 : V
CC
+2.0V at pulse width≤20ns, which is measured at V
CC
.
*2 : -2.0V at pulse width≤20ns, which is measured at V
SS
.
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM372E3200CK
Min
-
-
KMM372E3280CK
Min
-
-
-
-
-
-
-
-
-
-
-10
-10
2.4
-
Max
1720
1540
100
1720
1540
1900
1720
30
1720
1540
10
10
-
0.4
Max
2260
2080
100
2260
2080
2080
1900
30
2260
2080
10
10
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-10
-10
2.4
-
I
CC1
* : Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
* : Extended Data Out Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
I
CC5
: Standby Current (RAS=CAS=W=Vcc-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I(
IL)
: Input Leakage Current (Any input 0≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
I(
OL)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤Vcc)
V
OH
: Output High Voltage Level (I
OH
= -5mA)
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle time,
t
HPC
.
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