EDI88512VA-RP
HI-RELIABILITY PRODUCT
512Kx8 Plastic Monolithic 3.3V SRAM CMOS
FEATURES
s
512Kx8 bit CMOS Static
s
Random Access Memory
• Access Times of 15, 17, 20, 25ns
• Extended Temperature Testing
s
36 lead JEDEC Approved Revolutionary Pinout
• Plastic SOJ (Package 319)
s
Single +3.3V (±10%) Supply Operation
WEDC's ruggedized plastic 512Kx8 SRAM that allows the user to
capitalize on the cost advantage of using a plastic component
while not sacrificing all of the reliability available in a full military
device.
Extended temperature testing is performed with the test patterns
developed for use on WEDC’s fully compliant 512Kx8 SRAMs.
WEDC fully characterizes devices to determine the proper test
patterns for testing at temperature extremes. This is critical
because the operating characteristics of a device change when it
is operated beyond the commercial temperature range. Using
commercial methods will not guarantee a devicee that operates
reliabily in the field at temperature extremes. Users of WEDC’s
ruggedized plastic benefit from WEDC’s extensive experience in
characterizing SRAMs for use in military systems.
WEDC’s ruggedized plastic SOJ is footprint compatible with
WEDC’s full military ceramic 36 pin SOJ.
FIG. 1
A0
A1
A2
A3
A4
CS
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE
A5
A6
A7
A8
A9
PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
PIN DESCRIPTION
I/O
0-7
A
0-18
WE
CS
OE
V
CC
V
SS
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power (+3.3V )
Ground
Not Connected
36 pin
Revolutionary
BLOCK DIAGRAM
Memory Array
A
Ø-18
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
Ø-7
WE
CS
OE
June 1999 Rev. 1
1
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
EDI88512VA-RP
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
A
(Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, T
J
0 to +70
-40 to +85
-55 to +125
-65 to +125
0.55
20
175
°C
°C
°C
°C
W
mA
°C
-0.5 to 7.0
Unit
V
OE
X
H
L
X
CS
H
L
L
L
WE
X
H
H
L
TRUTH TABLE
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
Data Out
Data In
Power
Icc
2
, Icc3
Icc
1
Icc
1
Icc
1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.2
-0.3
Typ
3.3
0
—
—
Max
3.6
0
Vcc +0.3
+0.8
Unit
V
V
V
V
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional op-
eration of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may affect device reliability.
CAPACITANCE
(T
A
= +25°C)
Parameter
Address Lines
Data Lines
Symbol
C
I
C
O
Condition
V
IN
= Vcc or Vss, f = 1.0MHz
V
IN
= Vcc or Vss, f = 1.0MHz
Max Unit
7
8
pF
pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
(V
CC
= 5V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
WE, CS = V
IL
, I
I/O
= 0mA, Min Cycle
CS
≥
V
IH
, V
IN
≤
V
IL
, V
IN
≥
V
IH
CS
≥
V
CC
-0.2V
V
IN
≥
Vcc -0.2V or V
IN
≤
0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
(15ns)
(20-55ns)
Conditions
Min
-2
-2
—
—
—
—
—
2.4
Max
2
2
170
160
50
10
0.4
—
Units
µA
µA
mA
mA
mA
mA
V
V
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480Ω
480Ω
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
V
SS
to 3.0V
5ns
1.5V
Figure 1
Q
255Ω
30pF
Q
255Ω
5pF
NOTE:
For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
2
EDI88512VA-RP
AC CHARACTERISTICS – READ CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0°C to +70°C)
Symbol
JEDEC
Alt.
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
EHQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
t
RC
t
AA
t
ACS
t
CLZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
0
0
7
3
0
0
7
0
0
7
7
15ns
Min
15
15
15
3
0
0
8
0
0
8
7
Max
Min
17
17
17
3
0
0
10
0
0
10
8
17ns
Max
Min
20
20
20
3
0
0
12
10
20ns
Max
Min
25
25
25
25ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0°C to +70°C)
Symbol
JEDEC
Alt.
t
AVAV
t
ELWH
t
ELEH
t
AVWL
t
AVEL
t
AVWH
t
AVEH
t
WLWH
t
WLEH
t
WHAX
t
EHAX
t
WHDX
t
EHDX
t
WLQZ
t
DVWH
t
DVEH
t
WHQX
t
WC
t
CW
t
CW
t
AS
t
AS
t
AW
t
AW
t
WP
t
WP
t
WR
t
WR
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
WLZ
15ns
Min
15
13
13
0
0
12
12
12
12
0
0
0
0
0
8
8
0
7
Max
Min
17
14
14
0
0
14
14
14
14
0
0
0
0
0
8
8
0
8
17ns
Max
Min
20
15
15
0
0
15
15
15
15
0
0
0
0
0
10
10
0
8
20ns
Max
Min
25
17
17
0
0
17
17
17
17
0
0
0
0
0
12
12
0
10
25ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
3
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
EDI88512VA-RP
FIG. 2
TIMING WAVEFORM - READ CYCLE
ADDRESS
t
AVAV
t
AVQV
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
CS
t
ELQV
t
ELQX
OE
t
EHQZ
t
AVQV
DATA I/O
t
AVQX
DATA 1
DATA 2
t
GLQV
t
GLQX
DATA I/O
t
GHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3
WRITE CYCLE - WE CONTROLLED
t
AVAV
ADDRESS
t
AVWH
t
ELWH
CS
t
WHAX
t
AVWL
WE
t
WLWH
t
DVWH
t
WHDX
DATA IN
DATA VALID
t
WLQZ
DATA OUT
HIGH Z
t
WHQX
WRITE CYCLE 1, WE CONTROLLED
FIG. 4
WRITE CYCLE - CS CONTROLLED
ADDRESS
t
AVAV
WS32K32-XHX
t
AVEH
t
ELEH
t
EHAX
t
AVEL
t
WLEH
t
DVEH
t
EHDX
CS
WE
DATA IN
DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
4
EDI88512VA-RP
FIG. 5
NORMALIZED OPERATING GRAPHS
ICC1 (20ns) vs Temp
14
13
220
210
ICC1 (ma)
Write Pulse Width (ns)
Write Pulse Width vs. Temp.
12
11
10
9
8
7
6
200
190
180
170
160
-55
25
Temp. (C)
125
-55
Temp. (C)
25
125
ICC3 vs. Temp
TAVQV vs. Temp
10
TAVQV (ns)
22
20
ICC3 (ma)
1
18
190
16
14
0.1
0.01
12
-55
25
Temp. (C)
125
-55
25
Temp. (C)
125
ICCDR vs. Temp
10
1
ICCDR (ma)
0.1
0.01
Normalized curves are offered as a
service to our customers. They are
not to be construed as a guarantee of
operating characterics.
Characteristics of actual devices will
vary.
0.001
-55
25
Temp. (C)
125
IDR, 2V
IDR, 3V
5
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
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