Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
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OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
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NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 0.4 (04-01-05)
PRODUCT PREVIEW
2
SMSC SIO1036
Super I/O with LPC Interface with FIR and Consumer IR Support
General Description
The SMSC SIO1036 is a 3.3V PC 99, PC2001 compliant Super I/O Controller. The SIO1036
implements the LPC interface, a pin reduced ISA interface which provides the same or better
performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 1 GPIO
pin.
The SIO1036 incorporates a Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP
support. The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and
ECP. The parallel port ChiProtect circuitry prevents damage caused by an attached powered printer
when the SIO1036 is not powered.
The SIO1036 offers a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI
CLKRUN# support, relocatable configuration ports, and three DMA channel options.
There is a dedicated Serial Infrared interface UART, which complies with IrDA v1.2 (Fast IR), HPSIR,
and ASKIR formats (used by Sharp and other PDAs), as well as Consumer IR. This can also be used
as a 2 pin UART.
The SIO1036 features Software Configurable Logic (SCL) for ease of use. SCL allows programmable
system configuration of key functions such as the parallel port and UART.
The SIO1036 supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides the
recommended functionality to support Windows operating systems, PC99, and PC2001. The I/O
Address, DMA Channel, and Hardware IRQ of each device in the SIO1036 may be reprogrammed
through the internal configuration registers. There are multiple I/O address location options, a
Serialized IRQ interface, and three DMA channels.
PD[0:7],
MULTI-MODE
PARALLEL
PORT
BUSY, SLCT,
PE, nERROR, nACK
nSLCTIN, nALF
nINIT, nSTROBE
WDT
SMI
CONTROL, ADDRESS, DATA
GPIO*
GENERAL
PURPOSE
I/O
SER_IRQ
PCI_CLK
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
LPCPD#
CLKRUN#
SERIAL
IRQ
CONFIGURATION
REGISTERS
LPC BUS
INTERFACE
INFRARED
INTERFACE
(IrCC 2.0)
and
2 Pin UART
IRTX, IRMODE*
IRRX, ALT_IRRX*
CLOCK
GEN
Vcc Vss
CLOCKI
*
Denotes Multifunction Pins
Figure 1 SIO1036 Block Diagram
SMSC SIO1036
PRODUCT PREVIEW
3
Revision 0.4 (04-01-05)
REVISION HISTORY
REVISION
DESCRIPTION
SEE SPEC FRONT PAGE FOR REVISION HISTORY
DATE
-
RELEASED BY
-
D
3
TERMINAL #1
IDENTIFIER AREA
(D1/2 X E1/2)
D1
e
D2
-
TERMINAL #1
IDENTIFIER AREA
(D/2 X E/2)
3
E1
E
E2
EXPOSED PAD
4
0.6(MAX)
36X L
0.6(MAX)
36X 0.2 MIN
36X b
2
CHAMFERED CORNERS
ARE OPTIONAL 4X
TOP VIEW
BOTTOM VIEW
4X 0°-12°
C
4
ccc C
A1
A3
A2
A
SIDE VIEW
D2 / E2 VARIATIONS
CATALOG PART
3-D VIEWS
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
AND TOLERANCES ARE:
DECIMAL
X.X
±0.1
X.XX ±0.05
X.XXX ±0.025
ANGULAR
±1°
THIRD ANGLE PROJECTION
80 ARKAY DRIVE
HAUPPAUGE, NY 11788
USA
DIM AND TOL PER ASME Y14.5M - 1994
MATERIAL
NAME
DRAWN
DATE
-
-
S.K.ILIEV
CHECKED
12/6/04
12/6/04
PACKAGE OUTLINE
36 TERMINAL QFN, 6x6mm BODY, 0.5mm PITCH
DWG NUMBER
FINISH
S.K.ILIEV
APPROVED
MO-36-QFN-6x6
STD COMPLIANCE
SHEET
REV
F
1 OF 1
PRINT WITH "SCALE TO FIT"
DO NOT SCALE DRAWING
SCALE
S.K.ILIEV
12/6/04
1:1
JEDEC: MO-220
SMSC SIO1036
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETER.
2. POSITION TOLERANCE OF EACH TERMINAL IS ± 0.05mm AT MAXIMUM MATERIAL CONDITION. DIMENSIONS
"b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE
TERMINAL TIP.
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED.
4. COPLANARITY ZONE APPLIES TO EXPOSED PAD AND TERMINALS.
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