Si5367
µ P - P
ROGRAMMABLE
P
RECISION
C
L O C K
M
ULTIPLIER
Features
Not recommended for new
designs. For alternatives, see the
Si533x family of products.
Generates any frequency from
2 kHz to 945 MHz and select
frequencies to 1.4 GHz from an
input frequency of 10 to 710 MHz
Low jitter clock outputs w/jitter
generation as low as 0.6 ps rms
(50 kHz–80 MHz)
Integrated loop filter with
selectable loop bandwidth
(150 kHz to 1.3 MHz)
Four clock inputs with manual or
automatically controlled
switching
Five clock outputs with selectable
signal format (LVPECL, LVDS,
CML, CMOS)
Support for ITU G.709 FEC ratios
(255/238, 255/237, 255/236)
LOS alarm outputs
I
2
C or SPI programmable
settings
On-chip voltage regulator for
1.8 V ±5%, 2.5 V ±10%, or
3.5 V ±10% operation
Small size: 14 x 14 mm 100-pin
TQFP
Pb-free, RoHS compliant
Ordering Information:
See page 73.
Applications
SONET/SDH OC-48/OC-192 STM-
16/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line
cards
ITU G.709 and custom FEC line
cards
Wireless base stations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
Description
The Si5367 is a low jitter, precision clock multiplier for applications requiring clock
multiplication without jitter attenuation. The Si5367 accepts four clock inputs
ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs
ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device
provides virtually any frequency translation combination across this operating
range. The outputs are divided down separately from a common source. The
Si5367 input clock frequency and clock multiplication ratio are programmable
through an I
2
C or SPI interface. The Si5367 is based on Silicon Laboratories' 3rd-
generation DSPLL
®
technology, which provides any-frequency synthesis in a
highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a
single 1.8, 2.5, or 3.5 V supply, the Si5367 is ideal for providing clock
multiplication in high performance timing applications.
Rev. 0.5 2/12
Copyright © 2012 by Silicon Laboratories
Si5367
Si5367
Functional Block Diagram
CKIN1
CKIN2
÷ N31
÷ N32
÷ N33
÷ N34
÷ N2
÷ NC3_LS
CKOUT3
÷ NC1_LS
CKOUT1
CKIN3
CKIN4
DSPLL
®
N1_HS
÷ NC2_LS
CKOUT2
÷ NC4_LS
I
2
C/SPI Port
Clock Select
Device Interrupt
LOS Alarms
Control
÷ NC5_LS
CKOUT4
CKOUT5
VDD (1.8 or 2.5 V)
GND
2
Rev. 0.5
Si5367
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6. Pin Descriptions: Si5367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8. Package Outline: 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
10.1. Si5367 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Rev. 0.5
3
Si5367
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Supply Voltage during
Normal Operation
Symbol
T
A
V
DD
3.3 V Nominal
2.5 V Nominal
1.8 V Nominal
Test Condition
Min
–40
2.97
2.25
1.71
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
C
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
SIGNAL +
Differential I/Os V , V
OCM
ICM
SIGNAL –
V
V
ISE
, V
OSE
Single-Ended
Peak-to-Peak Voltage
(SIGNAL +) – (SIGNAL –)
V
ID
,V
OD
V
ICM
, V
OCM
t
Differential Peak-to-Peak Voltage
SIGNAL +
V
ID
= (SIGNAL+) – (SIGNAL–)
SIGNAL –
Figure 1. Differential Voltage Characteristics
80%
CKIN, CKOUT
20%
t
F
t
R
Figure 2. Rise/Fall Time Characteristics
4
Rev. 0.5
Si5367
Table 2. DC Characteristics
(V
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
A
=
–40 to 85 °C)
Parameter
Supply Current
1,2
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
Disable Mode
Min
—
Typ
394
Max
435
Unit
mA
—
253
284
mA
—
278
321
mA
—
229
261
mA
—
165
—
mA
CKINn Input Pins
3
Input Common Mode
Voltage (Input Thresh-
old Voltage)
Input Resistance
Single-Ended Input
Voltage Swing
(See Absolute Specs)
V
ICM
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
CKN
RIN
V
ISE
Single-ended
f
CKIN
< 212.5 MHz
See Figure 1.
f
CKIN
> 212.5 MHz
See Figure 1.
V
ID
f
CKIN
< 212.5 MHz
See Figure 1.
fCKIN > 212.5 MHz
See Figure 1.
0.9
1
1.1
20
0.2
0.25
0.2
0.25
—
—
—
40
—
—
—
—
1.4
1.7
1.95
60
—
—
—
—
V
V
V
k
V
PP
V
PP
V
PP
V
PP
Differential Input
Voltage Swing
(See Absolute Specs)
Output Clocks (CKOUTn)
4,5
Notes:
1.
Current draw is independent of supply voltage.
2.
The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
3.
No under- or overshoot is allowed.
4.
LVPECL outputs require nominal VDD
≥
2.5 V.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6.
This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
Rev. 0.5
5
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