®
HSP45116A
Data Sheet
May 7, 2007
FN4156.4
Numerically Controlled Oscillator/
Modulator
The Intersil HSP45116A combines a high performance
quadrature numerically controlled oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a
complex vector to be multiplied by the internally generated
(cos, sin) vector for quadrature modulation and
demodulation. As shown in the Block Diagram, the
HSP45116A is divided into three main sections. The Phase/
Frequency Control Section (PFCS) and the Sine/Cosine
Section together form a complex NCO. The CMAC multiplies
the output of the Sine/ Cosine Section with an external
complex vector.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.013Hz at 52MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 20-bit output ports which maintain
the 90dB spectral purity. This result can be accumulated
internally to implement an accumulate and dump filter.
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be down converted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal. The bit
position and widths for the outputs of CMAC and Complex
Accumulator (ACC) are programmable.
Features
• NCO and CMAC on One Chip
• 52MHz Version
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.013Hz Tuning Resolution at 52MHz
• Programmable Rounding Option
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
PART NUMBER
HSP45116AVC-52
PART MARKING
HSP45116AVC-52
TEMP. RANGE (°C)
0 to +70
0 to +70
PACKAGE
160 Ld MQFP (28mmx28mm)
160 Ld MQFP (28mmx28mm) (Pb-free)
PKG. DWG. #
Q160.28x28
Q160.28x28
HSP45116AVC-52Z (Note) HSP45116AVC-52Z
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HSP45116A
Block Diagram
VECTOR INPUT
R
I
SINE/
COSINE
ARGUMENT
MICROPROCESSOR
INTERFACE
INDIVIDUAL
CONTROL SIGNALS
PHASE/
FREQUENCY
CONTROL
SECTION
SIN
SINE/
COSINE
SECTION
COS
CMAC
R
I
VECTOR OUTPUT
2
FN4156.4
May 7, 2007
HSP45116A
Pinout
HSP45116A
(160 LD MQFP)
TOP VIEW
NC
V
CC
IMIN1
GND
IMIN2
IMIN3
IMIN4
IMIN5
IMIN6
IMIN7
IMIN8
IMIN9
IMIN10
IMIN11
IMIN12
V
CC
IMIN13
GND
IMIN14
IMIN15
IMIN16
IMIN17
IMIN18
IO19
IO18
IO17
IO16
IO15
V
CC
GND
IO14
IO13
IO12
IO11
IO10
GND
V
CC
IO9
IO8
IO7
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
IMIN0
RIN18
RIN17
RIN16
RIN15
RIN14
GND
RIN13
RIN12
RIN11
RIN10
RIN9
RIN8
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2
GND
RIN1
V
CC
RIN0
SH1
SH0
ACC
ENPHREG
ENOFREG
PEAK
RBYTILD
BINFMT
GND
TICO
V
CC
MOD1
MOD0
PACI
LOAD
PMSEL
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
GND
IO6
IO5
IO4
IO3
GND
IO2
IO1
V
CC
IO0
RO19
GND
RO18
RO17
RO16
RO15
RO14
V
CC
RO13
RO12
RO11
GND
RO10
RO9
V
CC
RO8
RO7
GND
RO6
RO5
RO4
RO3
V
CC
RO2
RO1
RO0
GND
DET1
DET0
CLROFR
ENCFREG
ENPHAC
ENTIREG
ENI
MODPI/2PI
CS
GND
CLK
V
CC
AD1
AD0
WR
C15
C14
C13
C12
C11
C10
C9
C8
GND
C7
C6
C5
C4
C3
C2
C1
C0
OUTMUX1
OUTMUX0
GND
OER
RND
OEREXT
OEIEXT
OEI
PACO
NC
3
FN4156.4
May 7, 2007
HSP45116A
Pin Descriptions
NAME
V
CC
NUMBER
22, 34, 50, 87, 95,
102, 111, 124, 132,
145, 159
7, 20, 32, 48, 62, 73,
83, 92, 98, 108,
114, 119, 125, 131,
143, 157
54-61, 63-70
51, 52
47
53
TYPE
-
+5V Power supply input.
DESCRIPTION
GND
-
Power supply ground input.
C0-15
AD0-1
CS
WR
I
I
I
I
Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
Address pins for selecting destination of C0-15 data. AD1 is the MSB.
Chip select (active low).
Write Enable. Data is clocked into the input register selected by AD0-1 on the rising edge of WR
when the CS line is low.
Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.
Phase Register Enable (active low). Registered on chip by CLK. When active low, after being
clocked onto chip, ENPHREG enables the clocking of data into the Phase Register.
Frequency Offset Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of frequency offset data into the frequency
offset register.
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the Center Frequency Register.
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the Phase Accumulator Register.
Time Interval Control Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENTIREG enables clocking of data into the Time Accumulator Register.
Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.
Modulo
π/2π
Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360
degrees). When high, the most significant address bit is held low so that the ROMs are addressed
modulo
π
(180 degrees). This input is registered on chip by clock. This control pin was included
for FFT processing.
Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the Frequency Offset Register
to the frequency adder. New data can still be clocked into the Frequency Offset Register;
CLROFR does not affect the contents of the register.
Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback path
in the phase accumulator without clearing the Phase Accumulator Register.
External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90, 180,
or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of the phase
control path are set to zero.
These bits are loaded into the Phase Register when ENPHREG is low.
MOD1
0
0
1
1
MOD0
0
1
0
1
PHASE SHIFT (DEGREES)
0
90
270
180
CLK
49
I
ENPHREG
27
I
ENOFREG
28
I
ENCFREG
42
I
ENPHAC
43
I
ENTIREG
44
I
ENI
45
I
MODPI/2PI
46
I
CLROFR
41
I
LOAD
38
I
MOD0-1
35, 36
I
4
FN4156.4
May 7, 2007
HSP45116A
Pin Descriptions
NAME
PMSEL
(Continued)
TYPE
I
DESCRIPTION
Phase Modulation Select Line. This line determines the source of the data clocked into the Phase
Register. When high, the Phase Control Register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the least
significant 14 bits are set to zero. This control is registered by CLK.
ROM Bypass, Timer Load (active low). Registered by CLK. This input bypasses the sine/ cosine
ROM so that the 16 bit phase adder output and lower 16 bits of the phase accumulator go directly
to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the Timer
Accumulator Register by zeroing the feedback in the accumulator.
Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to
increment by one in addition to the values in the Phase Accumulator Register and frequency
adder.
Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output
indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has
been reached.
Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low
when a carry is generated by the time interval accumulator. This function is provided to time out
control events such as synchronizing register clocking to data timing.
Real Input Data Bus. RIN18 is the MSB. This is the external real component into the complex
multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is asserted. Two’s
complement.
Imaginary Input Data Bus. IMIN18 is the MSB. This is the external imaginary component into the
complex multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is
asserted. Two’s complement.
Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the complex
multiplier. The shift controls are common to the shifters on both of the busses.
SH1
0
0
1
1
SH0
0
1
0
1
SELECTED BITS
RIN0-15, IMIN0-15
RIN1-16, IMIN1-16
RIN2-17, IMIN2-17
RIN3-18, IMIN3-18
NUMBER
39
RBYTILD
30
I
PACI
37
I
PACO
79
O
TICO
33
O
RIN0-18
2-6, 8-19, 21, 23
I
IMIN0-18
1, 138-142, 144,
146-156, 158
I
SH0-1
24, 25
I
ACC
26
I
Accumulate/Dump Control. This input controls the complex accumulators and their holding
registers. When high, the accumulators accumulate and the holding registers are disabled. When
low, the feedback in the accumulators is zeroed to cause the accumulators to load.
The holding registers are enabled to clock in the results of the accumulation. This input is
registered by CLK.
BINFMT
31
I
This input is used to convert the two’s complement output to offset binary (unsigned) for
applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal
two’s complement representation. This input is registered by CLK.
This input enables the peak detect feature of the block floating point detector. When high, the
maximum bit growth in the Output Holding Registers is encoded and output on the DET0-1 pins.
When the PEAK input is asserted, the block floating point detector output will track the maximum
growth in the holding registers, including the data in the Holding Registers at the time that PEAK
is activated.
PEAK
29
I
5
FN4156.4
May 7, 2007
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