DATASHEET
80C88
CMOS 8-/16-Bit Microprocessor
The Intersil
80C88
high performance 8-/16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS process
(Scaled SAJI IV). Two modes of operation, Minimum for small
systems and Maximum for larger applications such as
multiprocessing, allow user configuration to achieve the
highest performance level.
Full TTL compatibility (with the exception of CLOCK) and
industry-standard operation allow use of existing NMOS 8088
hardware and Intersil CMOS peripherals.
Complete software compatibility with the 80C86, 8086, and
8088 microprocessors allows use of existing software in new
designs.
FN2949
Rev.5.00
Sep 28, 2017
Features
• Compatible with NMOS 8088
• Direct software compatibility with 80C86, 8086, 8088
• 8-bit data bus interface; 16-bit internal architecture
• Completely static CMOS design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8MHz (80C88-2)
• Low power operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500µA maximum
- ICCOP. . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz maximum
• 1 MB of direct memory addressing capability
• 24 operand addressing modes
• Bit, byte, word, and block move operations
• 8-bit and 16-bit signed/unsigned arithmetic
• Bus-hold circuitry eliminates pull-up resistors
• Wide operating temperature ranges
- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
- M80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
• Pb-free available (RoHS compliant)
Related Literature
• For a full list of related documents, visit our website
-
80C88
product page
Ordering Information
PART NUMBER
(5MHz)
MD80C88/B
CP80C88Z
(Note)
PART
MARKING
MD80C88/B
CP80C88Z
CP80C88-2Z
PART NUMBER
(8MHz)
PART
MARKING
TEMPERATURE
RANGE
(°C)
-55 to +125
0 to +70
PACKAGE
40 LD CERDIP
40 LD PDIP*
(Pb-Free)
PKG. DWG. #
F40.6
E40.6
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2949 Rev.5.00
Sep 28, 2017
Page 1 of 39
80C88
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions (Minimum or Maximum Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions (Minimum Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description (Maximum Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Static Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Minimum and Maximum Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I/O Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Hold Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maskable Interrupt (INTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read/Modify/Write (Semaphore) Operations Via LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Synchronization Via TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Timing - Minimum System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Timing - Medium Complexity Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The 80C88 Compared to the 80C86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
13
13
13
14
14
14
14
14
15
15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Testing Input, Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Burn-In Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Metallization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Dual-In-Line Plastic Packages (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Ceramic Dual-In-Line Frit
Seal Packages (CERDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FN2949 Rev.5.00
Sep 28, 2017
Page 2 of 39
80C88
Pin Configurations
80C88
(40 LD PDIP, 40 LD CERIDP)
TOP VIEW
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MIN
MODE
40 V
CC
39 A15
38 A16/S3
37 A17/S4
36 A18/S5
35 A19/S6
34 SS0
33 MN/MX
32 RD
31 HOLD
30 HLDA
29 WR
28 IO/M
27 DT/R
26 DEN
25 ALE
24 INTA
23 TEST
22 READY
21 RESET
(RQ/GT0)
(RQ/GT1)
(LOCK)
(S2)
(S1)
(S0)
(QS0)
(QS1)
(HIGH)
MAX
MODE
FN2949 Rev.5.00
Sep 28, 2017
Page 3 of 39
80C88
Functional Diagram
EXECUTION UNIT
REGISTER FILE
DATA POINTER
AND
INDEX REGS
(8 WORDS)
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
16-BIT ALU
FLAGS
BUS
INTERFACE
UNIT
SSO/HIGH
4
8
8
3
4
A19/S6. . . A16/S3
AD7-AD0
A8-A15
INTA, RD, WR
DT/R, DEN, ALE, IO/M
4-BYTE
INSTRUCTION
QUEUE
TEST
INTR
NMI
RQ/GT0, 1
HOLD
HLDA
3
RESET READY MN/MX GND
V
CC
2
CONTROL AND TIMING
LOCK
2
3
QS0, QS1
S2, S1, S0
CLK
MEMORY INTERFACE
C-BUS
B-BUS
ES
BUS
INTERFACE
UNIT
CS
SS
DS
IP
INSTRUCTION
STREAM BYTE
QUEUE
EXECUTION UNIT
CONTROL SYSTEM
A-BUS
AH
BH
CH
EXECUTION
UNIT
DH
SP
BP
SI
DI
AL
BL
CL
DL
ARITHMETIC/
LOGIC UNIT
FLAGS
FN2949 Rev.5.00
Sep 28, 2017
Page 4 of 39
80C88
Pin Descriptions (Minimum or Maximum Mode)
The following pin function descriptions are for 80C88 systems in either Minimum or Maximum mode.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
MAXIMUM OR MINIMUM MODE. THE “LOCAL BUS” IN THESE DESCRIPTIONS IS THE DIRECT MULTIPLEXEDBUS INTERFACE CONNECTION TO THE 80C88
(WITHOUT REGARD TO ADDITIONAL BUS BUFFERS).
AD7 - AD0
9 - 16
I/O
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data (T2, T3,
Tw, and T4) bus. These lines are active HIGH and are held at high impedance to the last valid level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.
ADDRESS BUS: These lines provide address Bits 8 through 15 for the entire bus cycle (T1-T4). These lines do
not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high impedance to the
last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.
ADDRESS/STATUS: During T1, these are the four most
significant address lines for memory operations. During I/O
operations, these lines are LOW. During memory and I/O
operations, status information is available on these lines during
T2, T3, TW, and T4. S6 is always LOW. The status of the interrupt
enable flag bit (S5) is updated at the beginning of each clock
cycle. S4 and S3 are encoded as shown.
This information indicates which segment register is presently
being used for data accessing.
These lines are held at high impedance to the last valid logic level
during local bus “hold acknowledge” or “grant sequence”.
S4
0
0
1
1
S3
0
1
0
1
CHARACTERISTICS
Alternate Data
Stack
Code or None
Data
A15,
A14 -A8
A19/S6,
A18/S5,
A17/S4,
A16/S3
39, 2 - 8
O
35
36
37
38
O
O
O
O
RD
32
O
READ: The read strobe indicates that the processor is performing a memory or I/O read cycle, depending on
the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88 local bus. RD is
active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the 80C88 local
bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.
READY: The acknowledgment from the address memory or I/O device that it will complete the data transfer.
The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from READY. This signal
is active HIGH. The 80C88 READY input is not synchronized. Correct operation is not guaranteed if the set up
and hold times are not met.
INTERRUPT REQUEST: A level triggered input that is sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to
from an interrupt vector lookup table located in system memory. It can be internally masked by software
resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.
TEST: This input is examined by the “wait for test” instruction. If the TEST input is LOW, execution continues,
otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle
on the leading edge of CLK.
NONMASKABLE INTERRUPT: Edge triggered input which causes a type 2 interrupt. A subroutine is vectored
from an interrupt vector lookup table located in system memory. NMI is not maskable internally by software.
A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is
internally synchronized.
RESET: Cases the processor to immediately terminate its present activity. The signal must transition LOW to
HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the instruction
set description, when RESET returns LOW. RESET is internally synchronized.
CLOCK: Provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle
to provide optimized internal timing.
V
CC
: The +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for decoupling.
GND: Ground pins (both pins must be connected to system ground). A 0.1µF capacitor between pins 1 and 20
is recommended for decoupling.
READY
22
I
INTR
18
I
TEST
23
I
NMI
17
I
RESET
21
I
CLK
V
CC
GND
MN/MX
19
40
1, 20
33
I
I
MINIMUM/MAXIMUM: Indicates the mode in which the processor is to operate. The two modes are discussed
in the following sections.
FN2949 Rev.5.00
Sep 28, 2017
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