Data Sheet No. PD94119revA
IRU1010(PbF)
1A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
DESCRIPTION
The IRU1010 is a low dropout, three-terminal adjustable
regulator with minimum of 1A output current capability.
This product is specifically designed to provide well regu-
lated supply for low voltage IC applications such as high
speed bus termination and low current 3.3V logic sup-
ply. The IRU1010 is also well suited for other applica-
tions such as VGA and sound cards. The IRU1010 is
guaranteed to have <1.3V dropout at full load current
making it ideal to provide well regulated outputs of 2.5V
to 3.6V with 4.75V to 7V input supply.
FEATURES
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Built-In Thermal Shutdown
Available in SOT-223, D-Pak, Ultra Thin-Pak
TM
and 8-Pin SOIC Surface-Mount Packages
APPLICATIONS
VGA & Sound Card Applications
Low Voltage High Speed Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
D1
5V
C1
10uF
V
IN
3
2
1
R2
154
IRU1010
V
OUT
R1
121
C2
22uF
2.85V / 1A
Adj
Figure 1 - Typical application of IRU1010 in a 5V to 2.85V SCSI termination regulator.
PACKAGE ORDER INFORMATION
Basic Part (Non-Lead Free)
T
J
(°C)
0 To 150
2-PIN PLASTIC
TO-252 (D-Pak)
IRU1010CD
2-PIN PLASTIC
Ultra Thin-Pak
TM
(P)
IRU1010CP
8-PIN PLASTIC
SOIC (S)
IRU1010CS
3-PIN PLASTIC
SOT-223 (Y)
IRU1010CY
Leadfree Part
T
J
(°C)
0 To 150
Rev. 1.7
2-PIN PLASTIC
TO-252 (D-Pak)
Not available
2-PIN PLASTIC
Ultra Thin-Pak
TM
(P)
Not available
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8-PIN PLASTIC
SOIC (S)
IRU1010CSPbF
3-PIN PLASTIC
SOT-223 (Y)
Not available
1
IRU1010(PbF)
ABSOLUTE MAXIMUM RATINGS
Input Voltage (V
IN
) ....................................................
Power Dissipation .....................................................
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
7V
Internally Limited
-65°C To 150°C
0°C To 150°C
PACKAGE INFORMATION
2-PIN PLASTIC TO-252 (D-Pak)
FRONT VIEW
3
2-PIN ULTRA THIN-PAK
TM
(P)
FRONT VIEW
8-PIN PLASTIC SOIC (S)
TOP VIEW
3-PIN PLASTIC SOT-223 (Y)
TOP VIEW
V
IN
Tab is
V
OUT
3
V
IN
V
IN 1
NC
NC
Adj
2
3
4
8
7
6
5
Tab is
V
OUT
1
Adj
1
Adj
V
OUT
V
OUT
V
OUT
V
OUT
3
V
IN
V
OUT
Adj
Tab is
V
OUT
2
1
θ
JA
=708C/W for 0.5" Sq pad
θ
JA
=708C/W for 0.5" Sq pad
θ
JA
=558C/W for 1" Sq pad
θ
JA
=908C/W for 0.4" Sq pad
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over C
IN
=1µF, C
OUT
=10µF, and T
J
=0 to 1508C.
Typical values refer to T
J
=258C.
PARAMETER
Reference Voltage
Line Regulation
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Current Limit
Minimum Load Current (Note 3)
Thermal Regulation
Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change
Temperature Stability
Long Term Stability
RMS Output Noise
SYM
V
REF
TEST CONDITION
Io=10mA, T
J
=258C, (V
IN
-Vo)=1.5V
Io=10mA, (V
IN
-Vo)=1.5V
Io=10mA, 1.3V<(V
IN
-Vo)<7V
V
IN
=3.3V, V
ADJ
=0, 10mA<Io<1A
Note 2 , Io=1A
V
IN
=3.3V,
∆Vo=100mV
V
IN
=3.3V, V
ADJ
=0V
30ms Pulse, V
IN
-Vo=3V, Io=1A
f=120Hz, Co=25µF Tantalum,
Io=0.5A, V
IN
-Vo=3V
Io=10mA, V
IN
-Vo=1.5V, T
J
=258C,
Io=10mA, V
IN
-Vo=1.5V
Io=10mA, V
IN
-Vo=1.5V, T
J
=258C
V
IN
=3.3V, V
ADJ
=0V, Io=10mA
T
J
=1258C, 1000Hrs
T
J
=258C, 10Hz<f<10KHz
MIN
1.238
1.225
TYP
1.250
1.250
MAX
1.262
1.275
0.2
0.4
1.3
10
0.02
UNITS
V
%
%
V
A
mA
%/W
dB
120
5
1
µ
A
µ
A
%
%
%Vo
∆Vo
1.1
1.1
5
0.01
60
70
55
0.2
0.5
0.3
0.003
I
ADJ
Note 1:
Low duty cycle pulse testing with Kelvin con-
nections is required in order to maintain accurate data.
Note 2:
Dropout voltage is defined as the minimum dif-
ferential voltage between V
IN
and V
OUT
required to main-
tain regulation at V
OUT
. It is measured when the output
voltage drops 1% below its nominal value.
Note 3:
Minimum load current is defined as the mini-
mum current required at the output in order for the out-
put voltage to maintain regulation. Typically, the resistor
dividers are selected such that it automatically main-
tains this current.
2
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Rev. 1.7
IRU1010(PbF)
PIN DESCRIPTIONS
PIN #
1
2
3
PIN SYMBOL
Adj
V
OUT
V
IN
PIN DESCRIPTION
A resistor divider from this pin to the V
OUT
pin and ground sets the output voltage.
The output of the regulator. A minimum of 10µF capacitor must be connected from this pin
to ground to insure stability.
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum dropout
voltage during the load transient response. This pin must always be 1.3V higher than V
OUT
in order for the device to regulate properly.
BLOCK DIAGRAM
V
IN
3
2 V
OUT
+
1.25V
CURRENT
LIMIT
THERMAL
SHUTDOWN
+
1 Adj
Figure 2 - Simplified block diagram of the IRU1010.
APPLICATION INFORMATION
Introduction
The IRU1010 adjustable Low Dropout (LDO) regulator is
a three-terminal device which can easily be programmed
with the addition of two external resistors to any volt-
ages within the range of 1.25 to 5.5V. This regulator,
unlike the first generation of the three-terminal regula-
tors such as LM117 that required 3V differential between
the input and the regulated output, only needs 1.3V dif-
ferential to maintain output regulation. This is a key re-
quirement for today’s low voltage IC applications that
typically need 3.3V supply and are often generated from
the 5V supply. Other applications such as high speed
Rev. 1.7
memory termination need to switch the load current from
zero to full load in tens of nanoseconds at their pins,
which translates to an approximately 300 to 500ns cur-
rent step at the regulator. In addition, the output voltage
tolerances are sometimes tight and they include the tran-
sient response as part of the specification.
The IRU1010 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage, reducing the overall system cost with the
need for fewer output capacitors.
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3
IRU1010(PbF)
Output Voltage Setting
The IRU1010 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
V
OUT
= V
REF
3
1+
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+
R2/R1), or the effective resistance will be R
P(eff)
=R
P
3(1+
R2/R1). It is important to note that for high current appli-
cations, this can represent a significant percentage of
the overall load regulation and one must keep the path
from the regulator to the load as short as possible to
minimize this effect.
PARASITIC LINE
RESISTANCE
(
R2
R1
)
+I
ADJ
3R2
Where:
V
REF
= 1.25V Typically
I
ADJ
= 50µA Typically
R1 and R2 as shown in Figure 3:
V
IN
V
IN
V
OUT
R
P
IRU1010
V
IN
V
IN
V
OUT
Vout
Adj
IRU1010
Adj
V
REF
I
ADJ
= 50uA
R1
R1
R
L
R2
R2
Figure 4 - Schematic showing connection
for best load regulation.
Figure 3 - Typical application of the IRU1010
for programming the output voltage.
The IRU1010 keeps a constant 1.25V between the out-
put pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, add-
ing to the I
ADJ
current and into the R2 resistor producing
a voltage equal to the (1.25/R1)3R2+I
ADJ
3R2
which will
be added to the 1.25V to set the output voltage. This is
summarized in the above equation. Since the minimum
load current requirement of the IRU1010 is 10mA, R1 is
typically selected to be 121ς resistor so that it auto-
matically satisfies the minimum current requirement.
Notice that since I
ADJ
is typically in the range of 50µA it
only adds a small error to the output voltage and should
only be considered when a very precise output voltage
setting is required. For example, in a typical 3.3V appli-
cation where R1=121ς and R2=200ς the error due to
I
ADJ
is only 0.3% of the nominal set point.
Load Regulation
Since the IRU1010 is only a three-terminal device, it is
not possible to provide true remote sensing of the output
voltage at the load. Figure 4 shows that the best load
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the V
OUT
pin of the
regulator and not to the load. In fact, if R1 is connected
Stability
The IRU1010 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor ap-
plications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100mς and an output
capacitance of 500 to 1000µF. Fortunately as the ca-
pacitance increases, the ESR decreases resulting in a
fixed RC time constant. The IRU1010 takes advantage
of this phenomena in making the overall regulator loop
stable. For most applications a minimum of 100µF alu-
minum electrolytic capacitor such as Sanyo MVGX se-
ries, Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
Thermal Design
The IRU1010 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 1508C, it is recommended that the
selected heat sink be chosen such that during maxi-
mum continuous load operation the junction tempera-
ture is kept below this number. The next example for a
SCSI terminator application shows the steps in sellecting
the proper regulator in a surface-mount package. (See
IRU1015 for non-surface-mount packages)
4
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Rev. 1.7
IRU1010(PbF)
Assuming the following specifications:
V
IN
= 5V
V
F
= 0.5V
V
OUT
= 2.85V
I
OUT(MAX)
= 0.8A
T
A
= 358C
Where: V
F
is the forward voltage drop of the D1 diode as
shown in Figure 5.
The steps for selecting the right package with proper
board area for heatsinking to keep the junction tempera-
ture below 1358C is given as:
1) Calculate the maximum power dissipation using:
P
D
= I
OUT
3
(V
IN
- V
F
- V
OUT
)
P
D
= 0.8
3
(5 - 0.5 - 2.85) = 1.32W
2) Calculate the maximum
θ
JA
allowed for our example:
υ
JA(MAX)
=
T
J
- T
A
135 - 35
=
= 75.68C/W
P
D
1.32
Figure 5 - Final Schematic for half of the
GTL+ termination regulator.
Layout Consideration
The output capacitors must be located as close to the
V
OUT
terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the V
OUT
pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
5V
C1
10uF
To set the output DC voltage, we need to select R1 and
R2:
4) Assuming R1 = 121ς, 1%:
R
2
=
(
V
OUT
-1
V
REF
)
2.85
-1
3121
= 154.8ς
3R
1
=
1.25
(
)
Select R2 = 154ς, 1%.
D1
V
IN
V
OUT
2.85V
C2
22uF
R1
121
1%
R2
154
1%
IRU1010
Adj
3) Select a package from the datasheet with lower
θ
JA
than the one calculated in the previous step.
Selecting TO-252 (D-Pak) with at least 0.5" square
of 0.062" FR4 board using 1 oz. copper has 70
°
C/W
which is lower than the calculated number.
Rev. 1.7
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5
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